bigworm
Member level 3

I have tested the phase noise of PLL. the vco runs at 3.8GHz, and the probe is at the output of the divide-by-2.
the results show that there is a spur at frequency offset of 1MHz. the reference is 13MHz, and dividers are divide-by-2 and 8/9 divider.
I wonder how this spur comes? and also I noticed that the noise floor seems very high after frequency offset of 10M. it becomes flat rather than a slope.
why?
thank you.
the results show that there is a spur at frequency offset of 1MHz. the reference is 13MHz, and dividers are divide-by-2 and 8/9 divider.
I wonder how this spur comes? and also I noticed that the noise floor seems very high after frequency offset of 10M. it becomes flat rather than a slope.
why?
thank you.