how does this spur come from? (PLL)

[bigworm]

I have tested the phase noise of PLL. the vco runs at 3.8GHz, and the probe is at the output of the divide-by-2.
the results show that there is a spur at frequency offset of 1MHz. the reference is 13MHz, and dividers are divide-by-2 and 8/9 divider.
I wonder how this spur comes? and also I noticed that the noise floor seems very high after frequency offset of 10M. it becomes flat rather than a slope.
why?
thank you.

 

[biff44]

3800 MHz/13 MHz is not an integer. I suspect the pll is not set up like you stated.

 

[bigworm]

it is F-N PLL and the tuning rage of vco is 3700-3820MHz,

 

[biff44]

And there is your answer. The phase detector comparison frequency is.....?

 

[rfsystem]

If you observe an exact 1MHz spur and the reference is exact 13MHz you will have an periodicy of 13 reference cycles. That could only mean that your sigma-delta modulator does not generate good 8/9 divider sequences for the fractional division.

Is the 8/9 driven direct by sigma-delta at 32*13e6=416MHz or is there a swallow counter which is driven by the sigmal-delta at 13MHz?

If you can analyse the sigma-delta behaviour for the frequency setting where the spurs is you possible observe a digital limit cycle.