how does this serve as a d-cap ??

[chippi]

Hi,

Few doubts on CAPS

* what is called a "varactor cap" in mos ? is it the nwell-in-nmos cap that's called the varactor cap and how does the capacitance vary with respect to the gate voltage. and does the nwell in the nmos decrease ESR? if yes how ?

* how does the below figure act as a decap and what is the advantage of this type of a configuration compared to a single pmos/nmos cap? what is the total capacitance w.r.to VDD and VSS ( in terms of cgb/cgd/cgs)

 

[laglead]

The cap in your figure is mainly for thin gate oxide reliability concern. Under ESD event between power and gnd d-cap may be subjuect to high voltage. This kind of d-cap can avoid the gate oxide's direct facing ESD-induced high voltage. Of course it is not as efficient as conventional d-cap, due to the ESR.

 

[chippi]

hi laglead,

Could you plz explain how the attached figure works as a cap and it would be better if you can make a comparison with a single nmos-nwell cap and this cap.

 

[laglead]

hi laglead,

Could you plz explain how the attached figure works as a cap and it would be better if you can make a comparison with a single nmos-nwell cap and this cap.

Hi, chippi
The circuit in the figure has positive feedback and will be stable in a final state--- PMOS gate is pulled to ground by NMOS and NMOS gate is pulled to power by PMOS. Then the PMOS and NMOS gate oxide caps are used as d-cap. The only difference is that PMOS and NMOS drain-source resistance become ESR.

Can u make it clear what is the structure of nmos-nwell cap? Is it pmos-nwell instead?

 

[chippi]

hi laglead,

Firstly, i wanted to know the region in which the mos'es are operated in that configuration ?, At any point of the time what is the voltage at the gates of the pmos and nmos ?
else it would be really helpful, if u could suggest us any simulation setup which can help us understand this circuit better.

Secondly, i was talikng about the nwell in nmos cap. which looks like the one below, the nwell is used for nmos to have a substrate isolation and also this kind of a cap reduces the ESR.

 

[laglead]

Hi, Chippi,
NMOS gate is pulled to VDD and PMOS gate is pulled to VSS, so they are working in fully inversion region.
I have done the simulation with following steps (we denote NMOS as N1 and PMOS as P1):
1. use another nmos to pull down N1 gate to ground and another pmos to pull up P1 gate to power.
2. shut off nmos and pmos simultaneously.

N1's gate and P1's gate will gradually go to power and ground respectively due to loop's positive feedback.

If my simulation is not correct, please give your suggestion.

thanks

 

[chippi]

Hi LagLead,

Thanks for ur tip, it really helped.
and i need some more info :
i am actually comparing all possible CAP's which can be realised through MOS ( to be used as decoupling-caps)


* NMOS realised as CAP : GATE connected to VDD and S/D/B connected to VSS
(operated in deep inversion region )
* PMOS realised as CAP : GATE connected to VSS and S/D/B connected to VDD
(operated in deep inversion region )
* Nwell in NMOS CAP (AMOS) : GATE connected to VDD and S/D/B connected to VSS (operated in accumulation region )

If i try to simulate all the above three in schematic, to get the capacitance value
in 65nm tech,

NMOS (w=0.3, l=0.07u) , the cap value is 0.242fF
PMOS (w=0.3, l=0.07u) , the cap value is 2.08fF

i am not sure how to simulate the third one ( any idea ? )

My questions are,

1. if PMOS gives such a high value of CAP, y is that pmos is not preferred as a CAP.
I have heard that NWELL -NMOS cap gives the same value of cap as that of PMOS, how ? and also how can i verify that.

2. It would be helpful, if you could make a comparison for these three above caps in terms of
*capacitive density ( capcitance for the given area)
*leakage current
*ESR
and any other factors conisdered for MOS caps to be used as D-caps.

Any valuable information on this would be really helpful.

Thanks

Added after 1 hours 11 minutes:

 

[chippi]

Hi LagLead,

Thanks for ur tip, it really helped.
and i need some more info :
i am actually comparing all possible CAP's which can be realised through MOS ( to be used as decoupling-caps)


* NMOS realised as CAP : GATE connected to VDD and S/D/B connected to VSS
(operated in deep inversion region )
* PMOS realised as CAP : GATE connected to VSS and S/D/B connected to VDD
(operated in deep inversion region )
* Nwell in NMOS CAP (AMOS) : GATE connected to VDD and S/D/B connected to VSS (operated in accumulation region )

If i try to simulate all the above three in schematic, to get the capacitance value
in 65nm tech,

NMOS (w=0.3, l=0.07u) , the cap value is 0.242fF
PMOS (w=0.3, l=0.07u) , the cap value is 2.08fF

i am not sure how to simulate the third one ( any idea ? )

My questions are,

1. if PMOS gives such a high value of CAP, y is that pmos is not preferred as a CAP.
I have heard that NWELL -NMOS cap gives the same value of cap as that of PMOS, how ? and also how can i verify that.

2. It would be helpful, if you could make a comparison for these three above caps in terms of
*capacitive density ( capcitance for the given area)
*leakage current
*ESR
and any other factors conisdered for MOS caps to be used as D-caps.

Any valuable information on this would be really helpful.

Thanks

 

[laglead]

hi, chippi,
I have no much experience in on-chip mos cap usage, but hope my answers for your question is helpful:

1. If you refer to UMC or TSMC process application note, you will find data about MOS gate oxide gate cap values. I find similar values for NMOS and PMOS. Remember gate cap is determined maily by gate oxide thickness and it is the same for both types of transistor. Please re-examine you simulation. Due to the high mobility of electron, NMOS will have greated bandwidth than PMOS, So we prefer NMOS for decouping P/G noise with large frequency content. Sorry, I don't know nwell-nmos caps until you tell me.

2. Capacitance density and are determined by oxide. With the same gate area, PMOS de-cap has smaller leakage current than NMOS, because hole has to overcome higher potantial barrier to tunnel through. ESR is determined by transistor type and layout style. Generally, NMOS has low ESR than PMOS and large w/l ratio has low ESR than small w/l ratio (with same area).

Regards