Hi LagLead,
Thanks for ur tip, it really helped.
and i need some more info :
i am actually comparing all possible CAP's which can be realised through MOS ( to be used as decoupling-caps)
* NMOS realised as CAP : GATE connected to VDD and S/D/B connected to VSS
(operated in deep inversion region )
* PMOS realised as CAP : GATE connected to VSS and S/D/B connected to VDD
(operated in deep inversion region )
* Nwell in NMOS CAP (AMOS) : GATE connected to VDD and S/D/B connected to VSS (operated in accumulation region )
If i try to simulate all the above three in schematic, to get the capacitance value
in 65nm tech,
NMOS (w=0.3, l=0.07u) , the cap value is 0.242fF
PMOS (w=0.3, l=0.07u) , the cap value is 2.08fF
i am not sure how to simulate the third one ( any idea ? )
My questions are,
1. if PMOS gives such a high value of CAP, y is that pmos is not preferred as a CAP.
I have heard that NWELL -NMOS cap gives the same value of cap as that of PMOS, how ? and also how can i verify that.
2. It would be helpful, if you could make a comparison for these three above caps in terms of
*capacitive density ( capcitance for the given area)
*leakage current
*ESR
and any other factors conisdered for MOS caps to be used as D-caps.
Any valuable information on this would be really helpful.
Thanks
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