How does setup time impose maximum delay and hold time the minimum delay?

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ananth_anbu

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hi,
i have doubt in setup and hold time. Setup time imposes a maximum delay requirement, Hold time imposes a minimum delay requirement. How? ple. explain me
 

Re: setup and hold

this is because this are not tpd delay values.

for tco you will have maximum tpd time which is important.

however thold is imposed on the logic driving the part. i.e it has to have min. thold
time, the max is infinity.

for setup it is also imposed on driving device, since it now have to support certein tmax tpd to support the ts restriction, a minimum 0 tpd will be excellent.
 

    ananth_anbu

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Re: setup and hold

tco clock to output. (synchronous)
tpd propogation delay .(combinatoric).
 

Re: setup and hold

thanks for the reply......

but i need definition for the Tco and Tpd
 

Re: setup and hold

Plzz EDALIST and SHAWNDAKING...

* tco clock to output. is synchronous?? how??

explain me with an example

thanx in advance
 

setup and hold

This is because even the flipflop modeled is internally a combo logic and it requires some time delay for the input data to be latched to output
 

Re: setup and hold

This is because even the flipflop modeled is internally a combo logic and it requires some time delay for the input data to be latched to output
Click to expand...
What does it have to do with time for clock to output be synchronous?.FF's are synchronous...
Also Try this
You might wanna take a look at this for some basic info
**broken link removed**
If it's helpful enough,feedback here
 

setup and hold

GuyZ

Tco is simply the time between the rising/falling clock edge triggering the clk input of the FF and the appearance of the data at the FF output ..
In other words, the Q output of the FF doesn't appear instantaneousely once the clock edge triggers the clock input of the FF .. it takes time till the output appears .. this time is known as Tco ..
 

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