Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How does current starts to flow in short channel MOS?

Status
Not open for further replies.

branred

Newbie level 4
Joined
Oct 13, 2010
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,335
Dear all,

I have question regarding behaviour of short channel MOS

For a short channel MOS, if VDS is high, then DIBL will occur and this attract electrons from the source, thus current starts to flow. And isn't this analogy same as long channel MOS in saturation region? What are the differences?

Please correct me if anything is wrong and kindly enlighten me. All help is much appreciated. Thank you
 

Dear branred.

Very interesting question! In my point of view, there are similarities between these two phenomenon. The results of them are “similar” - higher current - but their causes seem to be different for me.

(a) Channel modulation: when the VDS voltage is so high that there isn’t the required voltage between the gate and channel (VG – VD) to cause the channel inversion. Therefore, there is the pinch-off and the channel length decreases with higher VDS.
(b) DIBL in small channel devices: the increase of the depletion region from the drain decreases the barrier for electron electron injection from source to drain. If drain voltage is too high, the depletion region of drain can reach the source (punch through).

I think that the effects caused by (b) are reduced in long channel devices, because the big values of transistor length. In this case, the drain and source regions are too distance each other in such way that the increase in the channel charges caused by increase in VDS is small compared with VGS. In other words, the depletion in the channel region is much more caused by gate voltage than drain voltage.

Phenomenon (a) is modeled by lambda
Phenomeon (b) is modeled by reduction of the threshold voltage.

This is my point of view. I´m not sure too.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top