How does clock latency affect setup and hold time?

[shweta.bphc]

Hi,

I would like to know how does clock latency affect setup and hold time? Does it help in any way?

 

[Simranjeet Singh]

Clock latency just means how much time it took for your clock signal to reach from clock generation point to sink. Ideally, the latency to all the sinks from a clock should be same, meaning all registers are receiving clocks at the same time. However, that is not the case, and hence we add buffers in certain clock paths to make sure the clock reaches all flops at the same time, to make sure that the latency for all the clock paths remain the same. So, to answer your question, yes, it does affect timing

 

[ThisIsNotSam]

Clock latency just means how much time it took for your clock signal to reach from clock generation point to sink. Ideally, the latency to all the sinks from a clock should be same, meaning all registers are receiving clocks at the same time. However, that is not the case, and hence we add buffers in certain clock paths to make sure the clock reaches all flops at the same time, to make sure that the latency for all the clock paths remain the same. So, to answer your question, yes, it does affect timing

This is old and outdated advice. You don't want clock signals to reach all flops at the same time, you want them to reach some flops early, and some late, therefore allowing paths to be dynamically relaxed or compressed depending on their needs. CTS is a multi goal step of the flow. Zero skew is a myth.