My guess is you didn't use enough substrate taps, and since your comparator is rapidly driving one side up and the other side down, you get injection, back bias, and crappy performace. i'd be surprised if it doesn't work at all, but bad performance i'd expect if layout is the problem..
another substrate resistance problem is latchup. as you build up voltage across the substrate, you can begin to turn on parasitic vertical devices. put a parasitic pnp (pmos) near an npn (nmos), and you get a free vertical SCR to click on and crowbar lots of current through your well.. DON'T DO THIS!
If you are worrying about how much voltage you are building up across the distributed substrate resistors, i think you are already in trouble - your layout needs substrate taps within 10-30um of any device (and well taps if you are using a twin-well process). absorb these carriers into metal 1 as quickly as possible, and you will be safer.
FYI - for the 1/2 micron analog process (twin well) that's most popular where I work, NMOS drivers sized 30/0.5 exhibited snapback (also caused by voltage across substrate) at 6v with well taps 20um away and 8v with well taps 5um away.