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How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input

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venn_ng

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Hi,

I am wondering if it makes sense to define a DNL/INL for a 1-bit delta sigma ADC (1-bit comparator) for a DC input? Since the data is processed after a digital filter and we could have a ±1 LSB error (meaning if the input is like 1LSB + Δv, we could have 1LSB or 2LSB at the output of delta-sigma without a 1-1 mapping due to limit cycles unlike other ADC architectures where is a 1-1 mapping), is there a way to define DNL/INL for a DC input? Does DNL/INL make sense?
 

sutapanaki

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I don't think it makes sense. All people do is look at the spectrum.
 

FvM

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INL/DNL is about static transfer characteristic deviations. 1-bit SD don't have it by design, except for possible nonlinearities of the analog modulator circuit.

Limit cycles, quantization noise and "tones" don't show in the static transfer characteristic.
 

    venn_ng

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