How do I write a verilog code to store different values at different times?

[keerthna]

I am trying to design a counter whose value might vary based on the frequency of the reference clock. So if I want to observe the count value for 5 cycles of time, how do I save those values?

for example if I have something like

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always@(posedge clk)
    begin
    count=count+1;
    if(count==some value)
    begin
    count=0;
    high=1;
    end
  if(high==1)
 begin
newcount1<=count2; // Count2 is another counter which detects the edges in a signal and                       increments. 
end
end

---

Now my problem is I want to observe the value of newcount1,newcount2newcount3,newcount4,newcount5 etc., so how do I store the values like this usine VERILOG?

 

[dipin]

hi

Now my problem is I want to observe the value of newcount1,newcount2newcount3,newcount4,newcount5 etc., so how do I store the values like this usine VERILOG?

i think you can store those values to a register.
declare a 2D array like [0:7]mem[0:8]

then

mem <= newcount1;
i<= i+1;

and i didnt know what you asked here

I am trying to design a counter whose value might vary based on the frequency of the reference clock

hope this helps

thanks & regards

 

[keerthna]

But my "newcount1" is a 32 bit register. So the value of this 32 bit register isn't going to the mem variable. Am i missing out something? please help. thanks in advance