how do i write a dual port memory code in vhdl?

[nmg]

can someone please guide me to write a write/read code for dual port memory in vhdl, i want the code to contain reset state, input state, write state and read state.and also i would want to include counters for address.

 

[TrickyDicky]

Well, for a start, if you have a reset, it cannot be a RAM.
Have a read of this document for templates for inferring ram in HDL code:
http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf

 

[nmg]

hi tnx
but keeping the states aside a simple read/write code how do i write it with address counters?
say this is my dual port ram code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity true_dual_port_ram is
  port (clk : in std_logic;
        we : in std_logic;
        en : in std_logic;
        addr1 : in std_logic_vector(5 downto 0);
        di1 : in std_logic_vector(15 downto 0);
        do1 : out std_logic_vector(15 downto 0));

        we2 : in std_logic;

        en2 : in std_logic;


        addr2 : in std_logic_vector(5 downto 0);
        di2 : in std_logic_vector(15 downto 0);
        do2 : out std_logic_vector(15 downto 0));


end true_dual_port_ram;



architecture ram_arch of true_dual_port_ram is

        type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
        signal RAM : ram_type;
begin

process (clk)
begin
        if clk'event and clk = '1' then
                if en = '1' then
                        if we = '1' then
                                RAM(conv_integer(addr)) <= di;
                        else
                                do <= RAM( conv_integer(addr));
                        end if;
                end if;
        end if;
end process;


process (clk)
begin
        if clk'event and clk = '1' then
                if en2 = '1' then
                        if we2 = '1' then
                                RAM(conv_integer(addr)) <= di2;
                        else
                                do2 <= RAM( conv_integer(addr));
                        end if;
                end if;
        end if;
end process;
end ram_arch;

 

[TrickyDicky]

Its a good start, add some counters for the addr and away you go.

 

[nmg]

thanks a ton!

 

[nmg]

can you please send an example code in which address counter are a part of read/write code.

 

[TrickyDicky]

Counters are a basic construct you can find in any tutorial. I suggest having a read of them.

signal count : unsigned(n downto 0);

process(clk, reset)
begin
  if reset = '1' then
    count <= (others => '0');
  elsif rising_edge(clk) then
    count <= count + 1;
  end if;
end process;

 

[nmg]

ok i do understand the counter but my question is how do i use the counter in the code that i've mentioned before??
do i just add the count statement before the read/write statement?

 

[FvM]

do i just add the count statement before the read/write statement?

Something like that.

Before you try, you should probably know which data do you want to read or write when. Also debug the various syntax errors in the copy and paste text shown in post #3.

 

[nmg]

ok i have this code with states is it correct?

entity bram is
port(clk:in std_logic;
       en1,en2:in std_logic;
       we1,we2:in std_logic_vector(o downto o);
        data:in std_logic_vector(31 downto 0);
        addr:in std_logic_vector(15 downto 0);
        dataouta,dataoutb:out std_logic_vector(31 downto 0));
end bram;
architecture behavioral of bram is
COMPONENT DPM
    PORT(clka:in std_logic;
             ena:in std_logic;
              wea:in std_logic_vector(0 downto 0);
              addra:in std_logic_vector(15 downto 0);
              dina:in std_logic_vector(31 downto 0);
              douta:out std_logic_vecor(31 downto 0);
              clkb:in std_logic;
              enb:in std_logic;
              web:in std_logic_vector(0 downto 0);
               addrb:in std_logic_vector(15 downto 0);
              dinb:in std_logic_vector(31 downto 0);
              doutb:out std_logic_vector(31 downto 0));
     END COMPONENT;
type state is (initial,input,writestate,readstate);
signal currentstate,nextstate:state;
signal addra,addrb:std_logic_vector(15 downto 0);
signal dina,dinb:std_logic_vector(31 downto 0);
signal wea,web:std_logic_vector(0 downto 0);
signal douta,doutb:std_logic_vector(31 downto o);
begin
our_instance_name:DPM
PORT MAP(
clka=>clk,
ena=>en1,
wea=>wea,
addra=>addra,
dina=>dina,
douta=>douta,
clkb=>clk,
enb=>en2,
web=>web,
addrb=>addrb,
dinb=>dinb,
doutb=>doutb);
process(clk,nextstate)
begin
if (clk'event and clk='1') then
case currentstate is
when initial=>
addra<="zzzzzzzzzzzzzzzz";
dina<="zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz";
addrb<="zzzzzzzzzzzzzzzz";
dinb<="00000000000000000000000000000000";
dataouta<="00000000000000000000000000000000";
dataoutb<="00000000000000000000000000000000";
if (en1='1')then
currentstate<=input;
else 
currentstate<=initial;
end if;
when input=>
wea<="1";
addra<=addr;
dina<=data;
if (we1=''1'') then
currentstate<=writestate;
else
currentstate<=initial;
end if;
when wriestate=>
if (addra="1111111111111111") then
currentstate<=initial;
else
wea<="0";
dataouta<=douta;
dataoutb<=doutb;
end if;
if (en2='1') then
if(we2="0") then
currentstate<=readstate;
web<="0";
addrb<=addra;
else
currentstate<=initial;
end if;
end if;
when readstate=>
currentstate<=writestate;
end case;
end if;
end process;
dataouta<=douta;
dataoutb<=doutb;
process(clk)
begin
if(clk='1') then
nextstate<=currentstate;
end if;
end process;
end behavioural;

 

[FvM]

i have this code with states is it correct?

It has errors. You need a VHDL simulator to check and correct it.

You previously planned to use an address counter that steps sequentially through addresses. It's missing from the code. I guess, you still didn't think exactly about the intended design operation. A timing diagram might be helpful.

If you have a homework problem/project specification, you should try to implement it. Otherwise you have to define what the problem exactly is.

 

[nmg]

basically i want a dual port ram write/read code with address counters and the above states(initial,input,read,write states)
can you please provide the code for it.?

 

[TrickyDicky]

It sounds like what you're trying to write is a FIFO. IP blocks for a fifo already exist..

 

[ads-ee]

If this is the OP's homework assignment. With a little searching on Google they could easily find papers on the topic of FIFO design. e.g. http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf

 

[FvM]

With a little searching on Google they could easily find papers on the topic of FIFO design.

And hopefully proceed from vague descriptions like "ram write/read code with address counters" to an explicite design specification.

 

[nmg]

ok, this code is what i've written

entity wriread is
    Port ( clk : in  STD_LOGIC;
           en1,en2 : in  STD_LOGIC;
           we1,we2 : in  STD_LOGIC_VECTOR (0 downto 0);
           data1,data2 : in  STD_LOGIC_VECTOR (31 downto 0);
           addr1,addr2 : in  STD_LOGIC_VECTOR (15 downto 0);
           datao1,datao2 : out  STD_LOGIC_VECTOR (31 downto 0));
end wriread;

architecture Behavioral of wriread is
type mem_type is array (0 downto 65535) of std_logic_vector(31 downto 0);
type state is (initial,input,write_initiate,write_complete);
signal mem:mem_type;
signal count: integer range 0 to 65535;
signal currentstate,nextstate:state;
begin
process(clk,currentstate)
begin
if(clk'event and clk='1') then
currentstate<=initial;
case currentstate is
when initial =>
   datao1<="00000000000000000000000000000000";
	datao2<="00000000000000000000000000000000";
   if (en1='1') then
    currentstate<=input;
  else
    currentstate<=initial;
  end if;
when input =>
   if(we1="1") then
	currentstate<=write_initiate;
	else
	currentstate<=initial;
   end if;
when write_initiate =>
   for count in 0 to 65535 loop
	mem(conv_integer(addr1))<=data1;
	end loop;
	currentstate<=write_complete;
when write_complete=>
   for count in 0 to 65535 loop
	datao1<=mem(conv_integer(addr1));
	end loop;
	end case;
	end if;
	end process;
	end Behavioral;

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but am getting an error
FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.16 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com

- - - Updated - - -

i am not able to fix it, can anyone tell me why?

 

[TrickyDicky]

Your loops are probably crashing it. Why do you even have the loops? they do the same thing 65536 times?

 

[nmg]

yup! now that i've made my data and address only 8bit and the counter ranging from 0 to 255, i have no errors, but when i run it it is getting stuck in line 37 (mem(conv_integer(addr1))<=data1
line 37 is my write statement, why do yo think its not getting any further than that?