So how do I understand this "if" in verilog ?
I thought that verilog is more simple to interpret the code.There's no simple one-to-one correspondence between single behavioral statement and structural description. You need to analyze the context. In case of the FF with clock enable, you have an implicit else that holds the previous state. The clock enable can be emulated by a mux.
I don't get it could you explain it again ?DFF is generated for each output bit of clocked always block (always_ff in your example). Combinational logic is generated for combinational and clocked blocks according to the logic expressions, no matter how they are described, e.g. logic operators, conditional code (if .. else), case construct, whatsoever. You need to decode the logic, e.g. write a truth table to see the final logic function.
// simple DFF
always_ff @(posedge clk)
q <= d;
// DFF with asynchronous reset
always_ff @(posedge clk, posedge reset)
if (reset)
q <= 1'b0;
else
q <= d;
// DFF with asynchronous reset and clock enable
always_ff @(posedge clk, posedge reset)
if (reset)
q <= 1'b0;
else if (enable)
q <= d;
Okey so if/else is to create DFF - as I understand this is a shortcut for D flipflop.clocked always block creates DFF, not the if statement. if statement is used to describe reset function and possibly clocke enable.
Code:// simple DFF always_ff @(posedge clk) q <= d; // DFF with asynchronous reset always_ff @(posedge clk, posedge reset) if (reset) q <= 1'b0; else q <= d; // DFF with asynchronous reset and clock enable always_ff @(posedge clk, posedge reset) if (reset) q <= 1'b0; else if (enable) q <= d;
Oooh so if I add more "if" statements in always_ff then I can have more clock enable ? so it is multiplexer connected to multiplexer ?i_e corresponds to enable in my example. I already explained how clock enable is emulated by a mux.
Not yet mentioned in your thread, which hardware are you synthesizing? If it's FPGA, most families have logic elements comprised of configurable 4 to 6 input LUT (look-up table) implementing the combinational logic, a DFF with different features (e.g. reset, possibly set, possibly dedicated clock enable) and static routing muxes.
Most synthesis tools can visualize both RTL and finally synthesized netlist. I was drawing the clock enable mux in post #2 because you only offered a basic DFF. The actual FPGA implementation may look different if the LE has a DFF with clock enable.
module alu(i_a, i_b, i_oper, o_y, o_zero);
parameter WIDTH = 2;
input logic [WIDTH-1:0] i_a, i_b;
input logic [1:0] i_oper;
output logic [WIDTH-1:0] o_y;
// Znacznik zera w wyniku
output logic o_zero;
always_comb
begin
{o_y, o_zero} = '0;
case(i_oper)
2'b00 : o_y = i_a + i_b;
2'b11 : o_y = i_a & i_b;
2'b01 : o_y = i_a - i_b;
default : o_y = 'd0;
endcase
if (~| o_y )
o_zero = '1;
end
endmodule
/* Generated by Yosys 0.9+4292 (git sha1 UNKNOWN, gcc 11.2.1 -O2 -fexceptions -fstack-protector-strong -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fPIC -Os) */
module alu(i_a, i_b, i_oper, o_y, o_zero);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
input [1:0] i_a;
input [1:0] i_b;
input [1:0] i_oper;
output [1:0] o_y;
output o_zero;
assign _00_ = ~i_a[0];
assign _01_ = ~i_b[0];
assign _02_ = ~i_oper[0];
assign _03_ = i_a[0] | _01_;
assign _04_ = _00_ ^ i_b[0];
assign _05_ = i_oper[1] | _04_;
assign _06_ = i_oper[0] & i_oper[1];
assign _07_ = i_a[0] & i_b[0];
assign _08_ = _06_ & _07_;
assign _09_ = ~_08_;
assign _10_ = _05_ & _09_;
assign o_y[0] = ~_10_;
assign _11_ = i_b[1] & i_a[1];
assign _12_ = _06_ & _11_;
assign _13_ = ~_12_;
assign _14_ = _02_ | i_oper[1];
assign _15_ = i_b[0] & _14_;
assign _16_ = i_b[1] ^ i_a[1];
assign _17_ = _15_ ^ _16_;
assign _18_ = _03_ ^ _17_;
assign _19_ = i_oper[1] | _18_;
assign _20_ = _13_ & _19_;
assign o_y[1] = ~_20_;
assign o_zero = _10_ & _20_;
endmodule
I wasn't sure exactly.I don't understand how you synthesize FPGA hardware without specifying a FPGA family.
I won't name the operation synthesis. Left and right side are functionally equivalent, it's just reordering of Verilog code. I realize that you don't understand how different Verilog text can represent the same logic function. I don't feel able to explain it within this thread.Left side is before synthezis and the right side is after syhtezis.
Please ;( I really don't know where to find this answer.I won't name the operation synthesis. Left and right side are functionally equivalent, it's just reordering of Verilog code. I realize that you don't understand how different Verilog text can represent the same logic function. I don't feel able to explain it within this thread.
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