How do I fix a too many BRAM COMP error in Spartan 6

[mlpin94]

I am presently working on Spartan 6 FPGA where i am using single bit ROM in IP Coregen. Here my .coe file is 80 kilobytes(120*120 image ) . But when i create a bit file it gives me an error saying "ERRORack:2310 - Too many comps of type "RAMB16BWER" found to fit this device." . What should i do. I am just using a rom for simple storage???

 

[rahdirs]

Re: IF ELSE Syntax error for Block RAM

But when i create a bit file it gives me an error saying "ERRORack:2310 - Too many comps of type "RAMB16BWER" found to fit this device." . What should i do. I am just using a rom for simple storage???

Hi,
How many BlockRAMs does your board have ?(16 - 20 ?)
Are you getting any error like this as well "The design is too large to fit the device" ?

 

[ads-ee]

You would have to be using a Spartan LX25 or larger to fit the amount of RAM (80KB or 640Kb) you are using.

LX25 has 52 RAMs for 936Kb total including the parity

LX45 116/2088Kb
LX75 172/3096Kb

etc..

If you are using some cheap eval board it probably has an LX9 or LX16 on it, which only has 32/576Kb of RAM so it doesn't fit.

 

[mlpin94]

Re: IF ELSE Syntax error for Block RAM

Hi,
How many BlockRAMs does your board have ?(16 - 20 ?)
Are you getting any error like this as well "The design is too large to fit the device" ?

yes i am getting this error
Pack:2310 - Too many comps of type "RAMB16BWER" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as
their packing might not have been completed.


My .coe file is 80 Kbytes and i am using Spartan 6 LX25 Board

 

[TrickyDicky]

The answer is rather obvious. Either use a bigger service or change your code.

You didn't post the code, so we can't help any more.

 

[ads-ee]

The answer is rather obvious. Either use a bigger service or change your code.

You didn't post the code, so we can't help any more.

Unless you provide code, and not just a small out of context snippet, but all the code that has RAMs or infers RAMs we can't help further.

You probably have some architecture that wastes BRAMs. BRAMs only come in 16Kb/18Kb chunks, so if your architecture doesn't fit the hardware resources then it just wastes the excess space and the design doesn't fit. Theoretically you should only need 40 BRAMs (80KB) if you pack the data properly.

BTW, you never provided the reported BRAM requirements from either MAP or Synthesis.

 

[mlpin94]

Unless you provide code, and not just a small out of context snippet, but all the code that has RAMs or infers RAMs we can't help further.

You probably have some architecture that wastes BRAMs. BRAMs only come in 16Kb/18Kb chunks, so if your architecture doesn't fit the hardware resources then it just wastes the excess space and the design doesn't fit. Theoretically you should only need 40 BRAMs (80KB) if you pack the data properly.

BTW, you never provided the reported BRAM requirements from either MAP or Synthesis.

I reduced the size of my image . I took a 64x64 image and the .coe came upto 18kb . Thank you all for helping me out. Finally i am done with my VGA controller

 

[mlpin94]

Now i have another issue . My vga is 640x480 and frequency is 25.175 MHz . But my Spartan 6 has a maximum of 4 MHz clock . What values of pixels do i need to take for in this case . I have a reference code which i am using :

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity VGAmain is
         port(
               F_CLK_4MHz              : in std_logic ;
             F_RESET                    : in std_logic;
             rgb                        : in std_logic_vector(7 downto 0);
             F_VER_SYNC           : out std_logic;
                F_HOR_SYNC           : out std_logic;
                pixelout             : out std_logic_vector(7 downto 0)
                );
end VGAmain;
 
architecture Behavioral of VGAmain is
 
signal hr_cnt           : std_logic_vector(9 downto 0); --for 1270 pixel cnt
signal vr_cnt           : std_logic_vector(9 downto 0); -- for 528 pixel cnt
--signal rgb_1,rgb_2    : std_logic_vector(7 downto 0);
signal hsync_s,clk_s : std_logic ;
signal clk_div      : std_logic_vector(20 downto 0);
--signal vsync_s : std_logic ;
signal temp_blank   : std_logic ;
begin
process(F_CLK_4MHz,F_RESET)
begin
 if(F_RESET = '1') then
    hr_cnt <= (others => '0');
 elsif(F_CLK_4MHz'event and F_CLK_4MHz = '1')then
    if(hr_cnt < 127)then
      hr_cnt <= hr_cnt + '1';
    else
      hr_cnt <= (others => '0');
    end if;
  end if ;
end process ;
 
process(hsync_s,F_RESET)
begin
 if(F_RESET = '1') then
    vr_cnt <= (others => '0');
 elsif(hsync_s'event and hsync_s = '1')then
    if(vr_cnt < 527)then
      vr_cnt <= vr_cnt + '1';
    else
      vr_cnt <= (others => '0');
    end if ;
end if ;
end process ;
 
F_HOR_SYNC <= hsync_s ;
 
process(F_CLK_4MHz,F_RESET)
begin
 if(F_RESET = '1') then
   hsync_s <= '1';
 elsif(F_CLK_4MHz'event and F_CLK_4MHz = '1')then
    if(hr_cnt >= 103 and hr_cnt < 118  )then
         hsync_s <= '0';
    else
        hsync_s <= '1';     
    end if ;
 end if ;
end process ;
 
process(hsync_s,F_RESET)
begin
 if(F_RESET = '1') then
   F_VER_SYNC <= '1';
 elsif(hsync_s'event and hsync_s = '1')then
    if(vr_cnt >= 490 and vr_cnt < 492)then
         F_VER_SYNC <= '0';
    else
         F_VER_SYNC <= '1';     
    end if ;
 end if ;
end process ;
 
 
--rgb_2 <= "11111111" when (vr_cnt < 66) else
--      "11111111" when (vr_cnt<=132) else
--      "00000000" when (vr_cnt<=198) else
--      "00000000" when (vr_cnt<=264) else
--      "11111111" when (vr_cnt<=330) else
--      "11111111" when (vr_cnt<=396) else
--      "00000000" when (vr_cnt<=462) else
--      "00000000";
--rgb_1 <= "11111111" when (hr_cnt < 15) else
--      "11111111" when (hr_cnt <= 30) else
--      "00000000" when (hr_cnt <= 45) else
--      "00000000" when (hr_cnt <= 60) else
--      "11111111" when (hr_cnt <= 75) else
--       "11111111" when (hr_cnt <= 90) else
--      "00000000" when (hr_cnt <= 105) else 
--      "00000000" ;
 
process(F_CLK_4MHz,F_RESET)
begin
    if (F_RESET = '1') then
        clk_div <= (others => '0');
    elsif (F_CLK_4MHz'event and F_CLK_4MHz = '1') then
        clk_div <= clk_div + 1;
    end if;
end process;
 
clk_s <= clk_div(14);
 
process(F_CLK_4MHz,rgb)
begin
    if (F_CLK_4MHz'event and F_CLK_4MHz = '1') then
        pixelout <= rgb;
    end if;
end process;
 
--rgb <= rgb_1 xor rgb_2;--cnt;
----rgb <= rgb_1; 
----rgb <= rgb_2; 
 
end Behavioral;

---

 

[rahdirs]

What values of pixels do i need to take for in this case .

What do you mean by this ?
Are you asking how to use Clocking wizard or something like that ?

 

[ads-ee]

Where does this 4 MHz clock come from? Did you divide some other clock to generate it?