Thanks for the response. I have a quick follow ups
I have done RTL to GDS flow for a project, but SDC, run script and all was already provided by professor. Now Im taking a random Open source RTL of a processor and trying to implement it from scratch.
1] Clock Period: I dont have the specs. How should I come up with a reasonable clock rate? If I go ambitious say ~0.3 nsec, it gives me large negative slack beyond a clock cycle. If I go around 1 nsec there is large positive slack. So should I stay in between and be reasonable and fix setup violations if there are any? Is trial and error the correct approach? I am using Synopsys Educational Libs.
2] Input/ Output Delay: Got it. For now I dont have a strict requirement. I can use approximate value, right?
3] MCP: Thanks for the explanation. Does that mean if these paths were not defined as MCPs they could have largest setup violations? And since we dont have any other way to run them within one clock cycle, we put them in MCPs. Can I use MCP concept to fix large negative slack which goes beyond a clock cycle, as discussed in 1] ?