How divide two numbers in verilog

[damla61]

Hi...


I want to write a module to compute x/y using divide operator where x and y are two signed numbers. Could anyone help me?

 

[permute]

what specifically are x,y?

If y is a constant, you can use a multiplication. (pre-compute 1/y), where 1/y * max(x) has good resolution.
otherwise, you'll need to use a division algorithm, of which there are many.

 

[damla61]

y is not a constant. But I am very new ın verilog and I don't know could you help me?

 

[happylbd]

you can use a divsion IP core to realize it
because division and multiplication can not systhesize in ISE or QUARTUS

 

[FvM]

because division and multiplication can not systhesize in ISE or QUARTUS

With Altera Quartus, a divider IP is automaticaly "inferred" from a signed x/y expression in Verilog or VHDL. With VHDL, the library IEEE.numeric_std is required for it. I don't know, if there's a similar feature in Xilinx IDE.

 

[Sudarsan_EDA]

Division requires one add/sub per result bit with a delay for the full
carry output before the next stage can begin. It's not a fast
algorithm

if suppose if you want devide a number with 4'd14,..
Rather than doing a divide by 4'd14,
consider doing a multiply by 17'h12492 which is 2^20/14. Your result
will be the product shifted by 20 bits.

 

[damla61]

thanksfor your helps..