If y is a constant, you can use a multiplication. (pre-compute 1/y), where 1/y * max(x) has good resolution.
otherwise, you'll need to use a division algorithm, of which there are many.
With Altera Quartus, a divider IP is automaticaly "inferred" from a signed x/y expression in Verilog or VHDL. With VHDL, the library IEEE.numeric_std is required for it. I don't know, if there's a similar feature in Xilinx IDE.
Division requires one add/sub per result bit with a delay for the full
carry output before the next stage can begin. It's not a fast
algorithm
if suppose if you want devide a number with 4'd14,..
Rather than doing a divide by 4'd14,
consider doing a multiply by 17'h12492 which is 2^20/14. Your result
will be the product shifted by 20 bits.