How deeper can Silicon be etched?

[Lathas]

How deep can Silicon be etched (either wet or dry)? If I have a 500um Si wafer, is it possible to etch a trench with depth ~400um? What issues can we foresee in such a case?

 

[erikl]

For TSV (Through Silicon Vias) aspect ratios >≈ 20:1 are state of the art, AFAIK, and this is also possible for blind-vias (trenches).

Issues arise from temperature changes (stress), depending on which material such trenches are filled with.

 

[dick_freebird]

Wafers are often thinned post-fab for packaging and
a super deep trench, or a pattern of them, might be
limiting how thin you can go - 16 mils deep is thicker
than the thinned wafers I usually see (not a normal
silicon flow, though). I'd say you probably would not
thin below 1mm (25 mils) for mechanical integrity
reasons if deep trenches are pervasive.

With a trench that deep, and probably pushing the
max aspect ratio, integrity and consistency of refill
may be a problem. So too, strain effects from (at
aspect ratio of 20:1) a 20um wide dissimilar-TCE
filled trench. Those will push into an abutting device
maybe to the tune of 10um (?) with device behavior
impacts that are unlikely to be well controlled (the
trench fill is usually early and crude with no test or
monitor structures, although maybe a smart guy
in technology development would put some, somewhere -
but will it make it onto the WT key, and be used to
keep strain effects as-modeled, as-expected?