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How declare that only PGC1 and PGD1 are for ICSP with PIC24FJ64GA004?

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treez

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Hello,

I am using the PIC24FJ64GA004 and wish to use PGD1 and PGC1 for ICSP.
However, considering the pins that have PGD2, PGD3, PGC2, PGC3, ........i want to use these as digital i/o pins.

If i connect the programmer to PGD1 & PGC1 , then how will the PIC know that these are the ones in to which the programming signals are being sent?

(how can i "declare" PGC1 and PGD1 as the only ICSP pins?)

PIC24FJ64GA004 DATASHEET:
http://ww1.microchip.com/downloads/en/DeviceDoc/39881D.pdf
 

bigdogguru

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When using Normal ICSP any of the available PGDx/PGCx pairs can be used and require no special configuration.

Reference: PIC24F Family Reference Manual, Section 33. Programming and Diagnostics, Page: 33-2
33.2 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™)

In-Circuit Serial Programming (ICSP) is Microchip’s original solution to providing microcontroller
programming in the target application. Originally introduced for 8-bit PIC16 devices, it is used for
virtually all Microchip microcontrollers. ICSP is also the most direct method to program the
device, whether the controller is embedded in a system or loaded into a device programmer.

33.2.1 ICSP Interface

ICSP uses two pins as the core of its interface. The programming data line (PGD) functions as
both an input and an output, allowing programming data to be read in and device information to
be read out on command. The programming clock line (PGC) is used to clock in data and control
the overall process.

Most PIC24F devices have more than one pair of PGC and PGD pins; these are multiplexed with
other I/O or peripheral functions. Individual ICSP pin pairs are indicated by number (e.g.,
PGC1/PGD1, etc.), and are generically referred to as ‘PGCx’ and ‘PGDx’. The multiple
PGCx/PGDx pairs provide additional flexibility in system design by allowing users to incorporate
ICSP on the pair of pins that is least constrained by the circuit design. All PGCx and PGDx pins
are functionally tied together and behave identically, and any one pair can be used for successful
device programming. The only limitation is that both pins from the same pair must be used.
In addition to the PGCx and PGDx pins, ICSP requires that all voltage supply and ground pins
on the device must be connected, as well as voltage regulator pins (ENVREG or DISVREG). The
MCLR pin, which is used with PGCx to enter and control the programming process, must also be
connected to the programming device.

33.2.2 ICSP Operation

ICSP uses a combination of internal hardware and external control to program the target device.
Programming data and instructions are provided on PGD. ICSP uses a special set of 4-bit
commands to control the overall process, combined with standard PIC24F instructions to execute
the actual writing of the program memory. PGD also returns data to the external programmer
when responding to queries.
Control of the programming process is achieved by manipulating PGC and MCLR. Entry into and
exit from Programming mode involves applying (or removing) voltage to MCLR while supplying a
code sequence to PGD and a clock to PGC. Any one of the PGCx/PGDx pairs can be used to enter
programming. During programming, the clock train on PGC is also used to indicate the difference
between 4-bit commands, programming control commands and payload data to be programmed.

When using Enhanced ICSP or ICD (Debugging) the selection of the required PGDx/PGCx pair is accomplished by properly setting the Configuration Register bits.

Refer to the device specific header file, p24FJ64GA004.h in this case:

Code:
**   Comm Channel Select:
**     ICS_PGx3             Emulator EMUC3/EMUD3 pins are shared with PGC3/PGD3
**     ICS_PGx2             Emulator EMUC2/EMUD2 pins are shared with PGC2/PGD2
**     ICS_PGx1             Emulator EMUC1/EMUD1 pins are shared with PGC1/PGD1
Note only a single invocation of CONFIG1 can occur in a project, therefore you will need to enable/disable any other features related to this macro represented by the dummy defines OPT2_OFF and OPT3_PLL.

Example of configuring PGD1/PGC1 for Enhanced ICSP or ICD:
Code:
CONFIG1( [COLOR="#FF0000"]ICS_PGx1[/COLOR] & OPT2_OFF & OPT3_PLL & ...)
p24FJ64GA004.h Configuration Register snippet:
Code:
/* -------------------------------------------------------- */
/* Macros for setting device configuration registers        */
/* -------------------------------------------------------- */

/* Register CONFIG2 (0xabfc)                               */

extern __attribute__((space(prog))) int _CONFIG2;
#define _CONFIG2(x) __attribute__((section("__CONFIG2.sec"),space(prog))) int _CONFIG2 = (x);

/*
** Only one invocation of CONFIG2 should appear in a project,
** at the top of a C source file (outside of any function).
**
** The following constants can be used to set CONFIG2.
** Multiple options may be combined, as shown:
**
** _CONFIG2( OPT1_ON & OPT2_OFF & OPT3_PLL )
**
**   Primary Oscillator Select:
**     POSCMOD_EC           EC Oscillator mode selected
**     POSCMOD_XT           XT Oscillator mode selected
**     POSCMOD_HS           HS Oscillator mode selected
**     POSCMOD_NONE         Primary oscillator disabled
**
**   I2C1 Pin Location Select:
**     I2C1SEL_SEC          Use alternate SCL1/SDA1 pins
**     I2C1SEL_PRI          Use default SCL1/SDA1 pins
**
**   IOLOCK Protection:
**     IOL1WAY_OFF          IOLOCK may be changed via unlocking seq
**     IOL1WAY_ON           Once IOLOCK is set, cannot be changed
**
**   Primary Oscillator Output Function:
**     OSCIOFNC_ON          OSC2/CLKO/RC15 functions as port I/O (RC15)
**     OSCIOFNC_OFF         OSC2/CLKO/RC15 functions as CLKO (FOSC/2)
**
**   Clock Switching and Monitor:
**     FCKSM_CSECME         Clock switching is enabled, Fail-Safe Clock Monitor is enabled
**     FCKSM_CSECMD         Clock switching is enabled, Fail-Safe Clock Monitor is disabled
**     FCKSM_CSDCMD         Clock switching and Fail-Safe Clock Monitor are disabled
**
**   Oscillator Select:
**     FNOSC_FRC            Fast RC Oscillator (FRC)
**     FNOSC_FRCPLL         Fast RC Oscillator with PLL module (FRCPLL)
**     FNOSC_PRI            Primary Oscillator (XT, HS, EC)
**     FNOSC_PRIPLL         Primary Oscillator with PLL module (HSPLL, ECPLL)
**     FNOSC_SOSC           Secondary Oscillator (SOSC)
**     FNOSC_LPRC           Low-Power RC Oscillator (LPRC)
**     FNOSC_FRCDIV         Fast RC Oscillator with Postscaler (FRCDIV)
**
**   Sec Oscillator Select:
**     SOSCSEL_LPSOSC       Low Power Secondary Oscillator (LPSOSC)
**     SOSCSEL_SOSC         Default Secondary Oscillator (SOSC)
**
**   Wake-up timer Select:
**     WUTSEL_FST           Fast Wake-up Timer
**     WUTSEL_LEG           Legacy Wake-up Timer
**
**   Internal External Switch Over Mode:
**     IESO_OFF             IESO mode (Two-Speed Start-up) disabled
**     IESO_ON              IESO mode (Two-Speed Start-up) enabled
**
*/

#define POSCMOD_EC           0xFFFC
#define POSCMOD_XT           0xFFFD
#define POSCMOD_HS           0xFFFE
#define POSCMOD_NONE         0xFFFF

#define I2C1SEL_SEC          0xFFFB
#define I2C1SEL_PRI          0xFFFF

#define IOL1WAY_OFF          0xFFEF
#define IOL1WAY_ON           0xFFFF

#define OSCIOFNC_ON          0xFFDF
#define OSCIOFNC_OFF         0xFFFF

#define FCKSM_CSECME         0xFF3F
#define FCKSM_CSECMD         0xFF7F
#define FCKSM_CSDCMD         0xFFBF

#define FNOSC_FRC            0xF8FF
#define FNOSC_FRCPLL         0xF9FF
#define FNOSC_PRI            0xFAFF
#define FNOSC_PRIPLL         0xFBFF
#define FNOSC_SOSC           0xFCFF
#define FNOSC_LPRC           0xFDFF
#define FNOSC_FRCDIV         0xFFFF

#define SOSCSEL_LPSOSC       0xEFFF
#define SOSCSEL_SOSC         0xFFFF

#define WUTSEL_FST           0xBFFF
#define WUTSEL_LEG           0xFFFF

#define IESO_OFF             0x7FFF
#define IESO_ON              0xFFFF

/* Register CONFIG1 (0xabfe)                               */

extern __attribute__((space(prog))) int _CONFIG1;
#define _CONFIG1(x) __attribute__((section("__CONFIG1.sec"),space(prog))) int _CONFIG1 = (x);

/*
** Only one invocation of CONFIG1 should appear in a project,
** at the top of a C source file (outside of any function).
**
** The following constants can be used to set CONFIG1.
** Multiple options may be combined, as shown:
**
** _CONFIG1( OPT1_ON & OPT2_OFF & OPT3_PLL )
**
**   Watchdog Timer Postscaler:
**     WDTPS_PS1            1:1
**     WDTPS_PS2            1:2
**     WDTPS_PS4            1:4
**     WDTPS_PS8            1:8
**     WDTPS_PS16           1:16
**     WDTPS_PS32           1:32
**     WDTPS_PS64           1:64
**     WDTPS_PS128          1:128
**     WDTPS_PS256          1:256
**     WDTPS_PS512          1:512
**     WDTPS_PS1024         1:1,024
**     WDTPS_PS2048         1:2,048
**     WDTPS_PS4096         1:4,096
**     WDTPS_PS8192         1:8,192
**     WDTPS_PS16384        1:16,384
**     WDTPS_PS32768        1:32,768
**
**   WDT Prescaler:
**     FWPSA_PR32           Prescaler ratio of 1:32
**     FWPSA_PR128          Prescaler ratio of 1:128
**
**   Watchdog Timer Window:
**     WINDIS_OFF           Windowed Watchdog Timer enabled; FWDTEN must be 1
**     WINDIS_ON            Standard Watchdog Timer enabled,(Windowed-mode is disabled)
**
**   Watchdog Timer Enable:
**     FWDTEN_OFF           Watchdog Timer is disabled
**     FWDTEN_ON            Watchdog Timer is enabled
**
**   Comm Channel Select:
**     ICS_PGx3             Emulator EMUC3/EMUD3 pins are shared with PGC3/PGD3
**     ICS_PGx2             Emulator EMUC2/EMUD2 pins are shared with PGC2/PGD2
**     ICS_PGx1             Emulator EMUC1/EMUD1 pins are shared with PGC1/PGD1
**
**   Set Clip On Emulation Mode:
**     COE_ON               Reset Into Clip On Emulation Mode
**     COE_OFF              Reset Into Operational Mode
**
**   Background Debug:
**     BKBUG_ON             Device resets into Debug mode
**     BKBUG_OFF            Device resets into Operational mode
**
**   General Code Segment Write Protect:
**     GWRP_ON              Writes to program memory are disabled
**     GWRP_OFF             Writes to program memory are allowed
**
**   General Code Segment Code Protect:
**     GCP_ON               Code protection is enabled for the entire program memory space
**     GCP_OFF              Code protection is disabled
**
**   JTAG Port Enable:
**     JTAGEN_OFF           JTAG port is disabled
**     JTAGEN_ON            JTAG port is enabled
**
*/

#define WDTPS_PS1            0x7FF0
#define WDTPS_PS2            0x7FF1
#define WDTPS_PS4            0x7FF2
#define WDTPS_PS8            0x7FF3
#define WDTPS_PS16           0x7FF4
#define WDTPS_PS32           0x7FF5
#define WDTPS_PS64           0x7FF6
#define WDTPS_PS128          0x7FF7
#define WDTPS_PS256          0x7FF8
#define WDTPS_PS512          0x7FF9
#define WDTPS_PS1024         0x7FFA
#define WDTPS_PS2048         0x7FFB
#define WDTPS_PS4096         0x7FFC
#define WDTPS_PS8192         0x7FFD
#define WDTPS_PS16384        0x7FFE
#define WDTPS_PS32768        0x7FFF

#define FWPSA_PR32           0x7FEF
#define FWPSA_PR128          0x7FFF

#define WINDIS_OFF           0x7FBF
#define WINDIS_ON            0x7FFF

#define FWDTEN_OFF           0x7F7F
#define FWDTEN_ON            0x7FFF

#define ICS_PGx3             0x7DFF
#define ICS_PGx2             0x7EFF
#define ICS_PGx1             0x7FFF

#define COE_ON               0x7FFF
#define COE_OFF              0x7FFF

#define BKBUG_ON             0x7FFF
#define BKBUG_OFF            0x7FFF

#define GWRP_ON              0x6FFF
#define GWRP_OFF             0x7FFF

#define GCP_ON               0x5FFF
#define GCP_OFF              0x7FFF

#define JTAGEN_OFF           0x3FFF
#define JTAGEN_ON            0x7FFF


#endif
Alternatively, you maybe able to use the MPLAB IDE Configuration Register Settings Window to accomplish this as well.



BigDog
 
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treez

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Thanks BigDogGuru,

The thing is, i dont need to do debugging, and i only want to use one set of PGC and PGD pins.......though are all the PGCX and PGDx pins tied together?

...i hope not, because that makes it difficult to use the duplicate pins for general IO?
 

keith1200rs

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No, the pins are not tied together. The CPU monitors them when the MCLR forces it into ICSP mode. There is no problem using the "unused PGC/PGD pins for I/O).

Keith.
 
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bigdogguru

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Notice in the quote previously posted:

All PGCx and PGDx pins
are functionally tied together and behave identically
, and any one pair can be used for successful
device programming. The only limitation is that both pins from the same pair must be used.
In addition to the PGCx and PGDx pins, ICSP requires that all voltage supply and ground pins
on the device must be connected, as well as voltage regulator pins (ENVREG or DISVREG). The
MCLR pin, which is used with PGCx to enter and control the programming process, must also be
connected to the programming device.
Microchip specifies the PGDx/PGCx pairs are "functionally tied together" NOT "physically tied together" therefore as Keith stated, used of the unused PGDx/PGCx pairs for their other multiplexed functions, like Digital I/O, is not an issue.

BigDog
 

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