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How could I reduce the 46 clocks latency in FSL bus?

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FuzzySNR

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FSL bus latency!

I am using the FSL bus to connect my IP to microblaze. By simulating the design in modelsim I found that each Write function call from C (Write-Read pair) to the FSL bus is made after 46 clocks from the last Write one while the Read operation happens on the next clock after the Write operation. Any ideas of why it takes so long, if it's normal, or how I could reduce the 46 clock latency whould be highly appreciated!
 

Re: FSL bus latency!

Anyone...??? Give us a hand here!!:D
 

Re: FSL bus latency!

The 46 cycles latency may correspond to other instructions microblaze is executing between successive FSL transactions. I think it is reasonable.
 

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