How can you reduce mismatch in BJT and MOS current mirrors?

[qwerty99]

Apart from following good layout techniques, are there any other methods?

 

[Warpspeed]

You can fit equal value emitter (or source) degeneration resistors to each device.
These need not be large, but the larger they are made, the better the balance.

 

[qwerty99]

How is degeneration helping to mitigate mismatch? Isn't it introducing more scope for mismatch as the values for resistors may not be same due to process variations?

 

[dick_freebird]

Of course then you add the resistor mismatch term
(hopefully better than MOS; likely so if MOS is small
and resistor is not challenging lithography).

Mismatch is driven down by more area (emitter for BJT;
W*L for MOS). In leading-edge minimum MOS, random
dopant (density) fluctuation is a big deal; I've seen it
said at conferences that some devices' channel doping
may be set by a single dopant atom. Hope both devices
got one. More area "evens it all out", doping, surface
states, all of it. But you pay in other ways.

For BJTs, beware the base current which will make Q2
collector (Iout) pull (Iin-2*(Iin/hFE). No biggy if you're
using BJTs with betas over 100 and don't care about
off by 2%. Let beta drop to 30 (like at low temp, off-
peak) and all of a sudden you care a lot more. Base
buffering, Wilson mirror are options.

Beware also Early voltage or lambda, which as
collector (drain) voltages mismatch, will drive the
current to mismatch as well. Cascode (or Wilson)
mirrors, there, at the cost of minimum output
voltage for decent fidelity.

Driving the "pilot" (Q1) device too hard, into
saturation, also will grossly mismatch things.