Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] How can you find an ideal target insertion delay before performing CTS?

Status
Not open for further replies.

iamcharlz

Newbie level 3
Newbie level 3
Joined
Sep 24, 2013
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
15
How can I find an ideal "target insertion delay" based on my design to enter before performing CTS?
 

You cannot... you can just estimate. Your target insertion delay should be such that your skew is not very high and for that you will have to do some dummy runs.
However, thumb rule says skew should be as low as possible. So for a design with 20MHz (50ns clock period) 0.5ns skew means 1% which might be acceptable depending on how prone your design is to timing violations. but the same 0.5ns for 200MHz would mean 10% violation and that in any design is not acceptable.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top