Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Take 2 shift registers, each 3 bits. Make each shift register a ring counter, so that Q feeds ino D.
Reset each of this 3 bit ring counters to a value of Q2Q1Q0 = 110.
When not in reset, it will work as a ring counter.
Now make one ring counter work on +ive edge of clk and the other on -ive edge.
Now your divby3clk is AND of Qs taken each from the 2 ring counters working on opposite clock. In fact you can take the o/p from an Q pair, like Qs or Qs