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How can the register number be different after synthesis in DC?

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tarkyss

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the same code
synthesis with dc
every the register number is same?
if different, why?
 

jjww110

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register number

perhaps something optimized
 

tarkyss

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register number

can you explain in detail?
can you show me some examples
 

johnli100

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Re: register number

After synthesis, the register number should always keep same, 'coz the dc optimization cannot remove registers.
 

incisive

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Re: register number

May be the logic inbetween has changed. Is there any difference when Library is changed?
 

AlexWan

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register number

Unloaded sequential cell will be removed when synthesis.

For example in DC, if you want to retain those cell, you have to do some setting:
set compile_delete_unloaded_sequential_cells false

By default, the value of this variable is true.
 

tarkyss

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register number

for example
for two different instances(maybe the same module but instance 2 times),
the same signal is connected the two instances, in the two instances, the signal is latched seperatly,
before synthesis, ungroup is excuted, the two register will be optimizated into one register?
 

AlexWan

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register number

No.
There are two registers in netlist with different name.
 

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