Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
for two different instances(maybe the same module but instance 2 times),
the same signal is connected the two instances, in the two instances, the signal is latched seperatly,
before synthesis, ungroup is excuted, the two register will be optimizated into one register?