[SOLVED] How can I write out .lib file of a digital module designed in virtuoso?

[wipshami]

Hi All

How can I write out .lib file of a digital module designed in virtuoso ?

Also If I want to import this module as a digital block to encounter, how can I make it as a macro/cell ? How to take care of this while

writing out lef from virtuoso ?



Thanks

Shameel

 

[rca]

Re: Writing out .lib & lef from virtuoso

from the layout tool, you should able to generate the asbtract which is the .lef file.
for the .lib file, you need a caracterization tool.

 

[wipshami]

Re: Writing out .lib & lef from virtuoso

The issue with lef is that once I export lef from virtuoso and read this to encounter,its not recognised by encounter as a macro.

Can we use the lef generated by File->Export->LEF in virtuoso directly to encounter ? Or anything else need to be done for generating abstract views so as to deal with the module as a macro in encounter?



Thanks

Shameel

 

[rca]

Re: Writing out .lib & lef from virtuoso

you need to change the "CLASS" attribut in the LEF file.
"CLASS BLOCK";

 

[wipshami]

Re: Writing out .lib & lef from virtuoso

Hi,

It has class attribut block. Still its not reading as MACRO. Please find the lef below

VERSION 5.7 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;

PROPERTYDEFINITIONS
MACRO oaTaper STRING ;
MACRO lastSavedExtractCounter INTEGER ;
LAYER LEF58_TYPE STRING ;
LAYER LEF58_SPACING STRING ;
LAYER LEF58_WIDTH STRING ;
END PROPERTYDEFINITIONS

UNITS
DATABASE MICRONS 1000 ;
END UNITS
MANUFACTURINGGRID 0.01 ;
LAYER OVERLAP
TYPE OVERLAP ;
END OVERLAP

LAYER NWEL
TYPE MASTERSLICE ;
PROPERTY LEF58_TYPE "TYPE NWELL ;" ;
PROPERTY LEF58_SPACING "SPACING 2.2 ;" ;
PROPERTY LEF58_WIDTH "WIDTH 0.9 ;" ;
END NWEL

LAYER DIFF
TYPE MASTERSLICE ;
END DIFF

LAYER PPLUS
TYPE IMPLANT ;
WIDTH 0.4 ;
SPACING 0.4 ;
END PPLUS

LAYER NPLUS
TYPE IMPLANT ;
WIDTH 0.4 ;
SPACING 0.4 ;
END NPLUS

LAYER PO1
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.4 0.4 ;
WIDTH 0.18 ;
AREA 0.198 ;
SPACING 0.34 ;
RESISTANCE RPERSQ 8 ;
PROPERTY LEF58_TYPE "TYPE POLYROUTING ;" ;
END PO1

LAYER CONT
TYPE CUT ;
SPACING 0.26 ;
WIDTH 0.24 ;
ENCLOSURE BELOW 0.1 0.1 ;
ENCLOSURE ABOVE 0 0.08 ;
END CONT

LAYER ME1
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.48 0.48 ;
WIDTH 0.24 ;
AREA 0.1764 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 0.24 0.28
WIDTH 9.999 0.28 0.28 ;
RESISTANCE RPERSQ 0.077 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME1

LAYER VI1
TYPE CUT ;
SPACING 0.28 ;
WIDTH 0.28 ;
ENCLOSURE BELOW 0.2 0.08 WIDTH 10 ;
ENCLOSURE BELOW 0 0.08 ;
ENCLOSURE ABOVE 0 0.08 ;
END VI1

LAYER ME2
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.56 0.56 ;
WIDTH 0.28 ;
AREA 0.1936 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 0.28 0.32
WIDTH 9.999 0.32 0.32 ;
RESISTANCE RPERSQ 0.062 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME2

LAYER VI2
TYPE CUT ;
SPACING 0.28 ;
WIDTH 0.28 ;
ENCLOSURE BELOW 0.2 0.08 WIDTH 10 ;
ENCLOSURE BELOW 0 0.08 ;
ENCLOSURE ABOVE 0 0.08 ;
END VI2

LAYER ME3
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.56 0.56 ;
WIDTH 0.28 ;
AREA 0.1936 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 0.28 0.32
WIDTH 9.999 0.32 0.32 ;
RESISTANCE RPERSQ 0.062 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME3

LAYER VI3
TYPE CUT ;
SPACING 0.28 ;
WIDTH 0.28 ;
ENCLOSURE BELOW 0.2 0.08 WIDTH 10 ;
ENCLOSURE BELOW 0 0.08 ;
ENCLOSURE ABOVE 0 0.08 ;
END VI3

LAYER ME4
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.56 0.56 ;
WIDTH 0.28 ;
AREA 0.1936 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 0.28 0.32
WIDTH 9.999 0.32 0.32 ;
RESISTANCE RPERSQ 0.062 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME4

LAYER VI4
TYPE CUT ;
SPACING 0.28 ;
WIDTH 0.28 ;
ENCLOSURE BELOW 0.2 0.08 WIDTH 10 ;
ENCLOSURE BELOW 0 0.08 ;
ENCLOSURE ABOVE 0 0.08 ;
END VI4

LAYER ME5
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.56 0.56 ;
WIDTH 0.28 ;
AREA 0.1936 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 0.28 0.32
WIDTH 9.999 0.32 0.32 ;
RESISTANCE RPERSQ 0.062 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME5

LAYER VI5
TYPE CUT ;
SPACING 0.28 ;
WIDTH 0.28 ;
ENCLOSURE BELOW 0.2 0.08 WIDTH 10 ;
ENCLOSURE BELOW 0 0.08 ;
ENCLOSURE ABOVE 0.4 0.4 ;
END VI5

LAYER ME6
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 2.2 2.2 ;
WIDTH 1.2 ;
AREA 9 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 1 1.5
WIDTH 9.999 1.5 1.5 ;
RESISTANCE RPERSQ 0.02 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME6

VIARULE M5_M6 GENERATE DEFAULT
LAYER ME5 ;
ENCLOSURE 0.08 0.08 ;
LAYER ME6 ;
ENCLOSURE 0.4 0.4 ;
LAYER VI5 ;
RECT -0.14 -0.14 0.14 0.14 ;
SPACING 0.56 BY 0.56 ;
END M5_M6

VIARULE M4_M5 GENERATE DEFAULT
LAYER ME4 ;
ENCLOSURE 0.08 0.08 ;
LAYER ME5 ;
ENCLOSURE 0.08 0.08 ;
LAYER VI4 ;
RECT -0.14 -0.14 0.14 0.14 ;
SPACING 0.56 BY 0.56 ;
END M4_M5

VIARULE M3_M4 GENERATE DEFAULT
LAYER ME3 ;
ENCLOSURE 0.08 0.08 ;
LAYER ME4 ;
ENCLOSURE 0.08 0.08 ;
LAYER VI3 ;
RECT -0.14 -0.14 0.14 0.14 ;
SPACING 0.56 BY 0.56 ;
END M3_M4

VIARULE M2_M3 GENERATE DEFAULT
LAYER ME2 ;
ENCLOSURE 0.08 0.08 ;
LAYER ME3 ;
ENCLOSURE 0.08 0.08 ;
LAYER VI2 ;
RECT -0.14 -0.14 0.14 0.14 ;
SPACING 0.56 BY 0.56 ;
END M2_M3

VIARULE M1_M2 GENERATE DEFAULT
LAYER ME1 ;
ENCLOSURE 0.08 0.08 ;
LAYER ME2 ;
ENCLOSURE 0.08 0.08 ;
LAYER VI1 ;
RECT -0.14 -0.14 0.14 0.14 ;
SPACING 0.56 BY 0.56 ;
END M1_M2

VIARULE M1_PDIFF GENERATE
LAYER DIFF ;
ENCLOSURE 0.1 0.1 ;
LAYER ME1 ;
ENCLOSURE 0.08 0.08 ;
LAYER CONT ;
RECT -0.12 -0.12 0.12 0.12 ;
SPACING 0.5 BY 0.5 ;
END M1_PDIFF

VIARULE M1_NWEL GENERATE
LAYER DIFF ;
ENCLOSURE 0.1 0.1 ;
LAYER ME1 ;
ENCLOSURE 0.08 0.08 ;
LAYER CONT ;
RECT -0.12 -0.12 0.12 0.12 ;
SPACING 0.5 BY 0.5 ;
END M1_NWEL

VIARULE M1_NDIFF GENERATE
LAYER DIFF ;
ENCLOSURE 0.1 0.1 ;
LAYER ME1 ;
ENCLOSURE 0.08 0.08 ;
LAYER CONT ;
RECT -0.12 -0.12 0.12 0.12 ;
SPACING 0.5 BY 0.5 ;
END M1_NDIFF

VIARULE M1_POLY GENERATE DEFAULT
LAYER PO1 ;
ENCLOSURE 0.1 0.1 ;
LAYER ME1 ;
ENCLOSURE 0.08 0.08 ;
LAYER CONT ;
RECT -0.12 -0.12 0.12 0.12 ;
SPACING 0.5 BY 0.5 ;
END M1_POLY

VIA M1_POLY_0
VIARULE M1_POLY ;
CUTSIZE 0.24 0.24 ;
LAYERS PO1 CONT ME1 ;
CUTSPACING 0.26 0.26 ;
ENCLOSURE 0.1 0.1 0.08 0.08 ;
ROWCOL 1 1 ;
END M1_POLY_0

VIA M1_POLY_1
VIARULE M1_POLY ;
CUTSIZE 0.24 0.24 ;
LAYERS PO1 CONT ME1 ;
CUTSPACING 0.26 0.26 ;
ENCLOSURE 0.1 0.1 0.08 0.08 ;
ROWCOL 1 1 ;
END M1_POLY_1

VIA M1_NWEL_2
VIARULE M1_NWEL ;
CUTSIZE 0.24 0.24 ;
LAYERS DIFF CONT ME1 ;
CUTSPACING 0.26 0.26 ;
ENCLOSURE 0.1 0.1 0.08 0.08 ;
ROWCOL 1 1 ;
END M1_NWEL_2

VIA M1_NWEL_3
VIARULE M1_NWEL ;
CUTSIZE 0.24 0.24 ;
LAYERS DIFF CONT ME1 ;
CUTSPACING 0.26 0.26 ;
ENCLOSURE 0.1 0.1 0.08 0.08 ;
ROWCOL 1 1 ;
END M1_NWEL_3

VIA M1_PDIFF_4
VIARULE M1_PDIFF ;
CUTSIZE 0.24 0.24 ;
LAYERS DIFF CONT ME1 ;
CUTSPACING 0.26 0.26 ;
ENCLOSURE 0.1 0.1 0.08 0.08 ;
ROWCOL 1 1 ;
END M1_PDIFF_4

VIA M1_PDIFF_5
VIARULE M1_PDIFF ;
CUTSIZE 0.24 0.24 ;
LAYERS DIFF CONT ME1 ;
CUTSPACING 0.26 0.26 ;
ENCLOSURE 0.1 0.1 0.08 0.08 ;
ROWCOL 1 1 ;
END M1_PDIFF_5

VIA M1_M2_6
VIARULE M1_M2 ;
CUTSIZE 0.28 0.28 ;
LAYERS ME1 VI1 ME2 ;
CUTSPACING 0.28 0.28 ;
ENCLOSURE 0.08 0.08 0.08 0.08 ;
ROWCOL 1 1 ;
END M1_M2_6

VIA M1_M2_7
VIARULE M1_M2 ;
CUTSIZE 0.28 0.28 ;
LAYERS ME1 VI1 ME2 ;
CUTSPACING 0.28 0.28 ;
ENCLOSURE 0.08 0.08 0.08 0.08 ;
ROWCOL 1 1 ;
END M1_M2_7

VIA M2_M3_8
VIARULE M2_M3 ;
CUTSIZE 0.28 0.28 ;
LAYERS ME2 VI2 ME3 ;
CUTSPACING 0.28 0.28 ;
ENCLOSURE 0.08 0.08 0.08 0.08 ;
ROWCOL 1 1 ;
END M2_M3_8

VIA M2_M3_9
VIARULE M2_M3 ;
CUTSIZE 0.28 0.28 ;
LAYERS ME2 VI2 ME3 ;
CUTSPACING 0.28 0.28 ;
ENCLOSURE 0.08 0.08 0.08 0.08 ;
ROWCOL 1 1 ;
END M2_M3_9

MACRO pseudo-nmos1
CLASS BLOCK ;
ORIGIN 18.2 10.7 ;
FOREIGN pseudo-nmos1 -18.2 -10.7 ;
SIZE 113.9 BY 138.4 ;
PIN c1
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0.2 74.8 0.4 75 ;
END
END c1
PIN c2
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0 49.1 0.5 49.34 ;
END
END c2
PIN c3
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0 51.2 0.4 51.44 ;
END
END c3
PIN c4
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0.3 26.8 0.6 27 ;
END
END c4
PIN D1
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0 4.5 0.5 4.74 ;
END
END D1
PIN D2
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0 3.5 0.3 3.74 ;
END
END D2
PIN D3
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0 2.7 0.4 2.94 ;
END
END D3
PIN D4
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0 1.8 0.3 2.04 ;
END
END D4
PIN vdd
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER ME1 ;
RECT 1.37 110.17 1.84 110.38 ;
END
PORT
LAYER ME1 ;
RECT 0 110.16 80.5 110.4 ;
END
END vdd
PIN gnd
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER ME1 ;
RECT 1.32 0.02 1.6 0.21 ;
END
PORT
LAYER ME1 ;
RECT 0 0 80.5 0.24 ;
END
END gnd
PIN vout
DIRECTION OUTPUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 41.66 70.68 41.9 70.92 ;
END
END vout
OBS
LAYER OVERLAP ;
POLYGON -13 -4.3 -13 120.1 89.5 120.1 89.5 -4.3 ;
END
PROPERTY oaTaper "__DerivedDefaultTaperCG" ;
PROPERTY lastSavedExtractCounter 1084 ;
END pseudo-nmos1

END LIBRARY

 

[rca]

Re: Writing out .lib & lef from virtuoso

the section before the MACRO key word which define the techno could be removed.

 

[wipshami]

Re: Writing out .lib & lef from virtuoso

Without that part it error out with " no technology definition ".

In the lef (written out after abstract generation from virtuoso) , If I change CLASS to PAD instead of CORE or BLOCK ,encounter is recognizing it as IO pad with pins and exactly how I needed it; except that it is IO .

But its not supporting CORE,BLOCK

Is there any attribute in lef that does n't support for CORE but IO ?

Thanks
Shameel

 

[rca]

Re: Writing out .lib & lef from virtuoso

to read the lef files in Encounter, first file of the LEF list must be the technology LEF file after that the macros LEF files.

 

[wipshami]

Re: Writing out .lib & lef from virtuoso

Hi,
Both technology and cell details are there in the single lef. Its not a problem . Encounter will read the lef even If we give it in single lef or as multiple lef.
I have no issues with reading but with reading as MACRO

Thanks
Shameel

 

[vimalraj205]

Re: Writing out .lib & lef from virtuoso

can you post your Macro lef & encounter log section in this if your problem is not solved yet

 

[wipshami]

Re: Writing out .lib & lef from virtuoso

Hi,

please find the lef and log below

*******lef*************
VERSION 5.7 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;

PROPERTYDEFINITIONS
MACRO oaTaper STRING ;
LAYER LEF58_TYPE STRING ;
LAYER LEF58_SPACING STRING ;
LAYER LEF58_WIDTH STRING ;
END PROPERTYDEFINITIONS

UNITS
DATABASE MICRONS 1000 ;
END UNITS
MANUFACTURINGGRID 0.01 ;
LAYER OVERLAP
TYPE OVERLAP ;
END OVERLAP

LAYER NWEL
TYPE MASTERSLICE ;
PROPERTY LEF58_TYPE "TYPE NWELL ;" ;
PROPERTY LEF58_SPACING "SPACING 2.2 ;" ;
PROPERTY LEF58_WIDTH "WIDTH 0.9 ;" ;
END NWEL

LAYER DIFF
TYPE MASTERSLICE ;
END DIFF

LAYER PPLUS
TYPE IMPLANT ;
WIDTH 0.4 ;
SPACING 0.4 ;
END PPLUS

LAYER NPLUS
TYPE IMPLANT ;
WIDTH 0.4 ;
SPACING 0.4 ;
END NPLUS

LAYER PO1
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.4 0.4 ;
WIDTH 0.18 ;
AREA 0.198 ;
SPACING 0.34 ;
RESISTANCE RPERSQ 8 ;
PROPERTY LEF58_TYPE "TYPE POLYROUTING ;" ;
END PO1

LAYER CONT
TYPE CUT ;
SPACING 0.26 ;
WIDTH 0.24 ;
ENCLOSURE BELOW 0.1 0.1 ;
ENCLOSURE ABOVE 0 0.08 ;
END CONT

LAYER ME1
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.48 0.48 ;
WIDTH 0.24 ;
AREA 0.1764 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 0.24 0.28
WIDTH 9.999 0.28 0.28 ;
RESISTANCE RPERSQ 0.077 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME1

LAYER VI1
TYPE CUT ;
SPACING 0.28 ;
WIDTH 0.28 ;
ENCLOSURE BELOW 0.2 0.08 WIDTH 10 ;
ENCLOSURE BELOW 0 0.08 ;
ENCLOSURE ABOVE 0 0.08 ;
END VI1

LAYER ME2
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.56 0.56 ;
WIDTH 0.28 ;
AREA 0.1936 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 0.28 0.32
WIDTH 9.999 0.32 0.32 ;
RESISTANCE RPERSQ 0.062 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME2

LAYER VI2
TYPE CUT ;
SPACING 0.28 ;
WIDTH 0.28 ;
ENCLOSURE BELOW 0.2 0.08 WIDTH 10 ;
ENCLOSURE BELOW 0 0.08 ;
ENCLOSURE ABOVE 0 0.08 ;
END VI2

LAYER ME3
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.56 0.56 ;
WIDTH 0.28 ;
AREA 0.1936 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 0.28 0.32
WIDTH 9.999 0.32 0.32 ;
RESISTANCE RPERSQ 0.062 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME3

LAYER VI3
TYPE CUT ;
SPACING 0.28 ;
WIDTH 0.28 ;
ENCLOSURE BELOW 0.2 0.08 WIDTH 10 ;
ENCLOSURE BELOW 0 0.08 ;
ENCLOSURE ABOVE 0 0.08 ;
END VI3

LAYER ME4
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.56 0.56 ;
WIDTH 0.28 ;
AREA 0.1936 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 0.28 0.32
WIDTH 9.999 0.32 0.32 ;
RESISTANCE RPERSQ 0.062 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME4

LAYER VI4
TYPE CUT ;
SPACING 0.28 ;
WIDTH 0.28 ;
ENCLOSURE BELOW 0.2 0.08 WIDTH 10 ;
ENCLOSURE BELOW 0 0.08 ;
ENCLOSURE ABOVE 0 0.08 ;
END VI4

LAYER ME5
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.56 0.56 ;
WIDTH 0.28 ;
AREA 0.1936 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 0.28 0.32
WIDTH 9.999 0.32 0.32 ;
RESISTANCE RPERSQ 0.062 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME5

LAYER VI5
TYPE CUT ;
SPACING 0.28 ;
WIDTH 0.28 ;
ENCLOSURE BELOW 0.2 0.08 WIDTH 10 ;
ENCLOSURE BELOW 0 0.08 ;
ENCLOSURE ABOVE 0.4 0.4 ;
END VI5

LAYER ME6
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 2.2 2.2 ;
WIDTH 1.2 ;
AREA 9 ;
SPACINGTABLE
PARALLELRUNLENGTH 0 9.999
WIDTH 0 1 1.5
WIDTH 9.999 1.5 1.5 ;
RESISTANCE RPERSQ 0.02 ;
MINIMUMDENSITY 25 ;
DENSITYCHECKWINDOW 1000 1000 ;
DENSITYCHECKSTEP 500 ;
END ME6

VIARULE M5_M6 GENERATE DEFAULT
LAYER ME5 ;
ENCLOSURE 0.08 0.08 ;
LAYER ME6 ;
ENCLOSURE 0.4 0.4 ;
LAYER VI5 ;
RECT -0.14 -0.14 0.14 0.14 ;
SPACING 0.56 BY 0.56 ;
END M5_M6

VIARULE M4_M5 GENERATE DEFAULT
LAYER ME4 ;
ENCLOSURE 0.08 0.08 ;
LAYER ME5 ;
ENCLOSURE 0.08 0.08 ;
LAYER VI4 ;
RECT -0.14 -0.14 0.14 0.14 ;
SPACING 0.56 BY 0.56 ;
END M4_M5

VIARULE M3_M4 GENERATE DEFAULT
LAYER ME3 ;
ENCLOSURE 0.08 0.08 ;
LAYER ME4 ;
ENCLOSURE 0.08 0.08 ;
LAYER VI3 ;
RECT -0.14 -0.14 0.14 0.14 ;
SPACING 0.56 BY 0.56 ;
END M3_M4

VIARULE M2_M3 GENERATE DEFAULT
LAYER ME2 ;
ENCLOSURE 0.08 0.08 ;
LAYER ME3 ;
ENCLOSURE 0.08 0.08 ;
LAYER VI2 ;
RECT -0.14 -0.14 0.14 0.14 ;
SPACING 0.56 BY 0.56 ;
END M2_M3

VIARULE M1_M2 GENERATE DEFAULT
LAYER ME1 ;
ENCLOSURE 0.08 0.08 ;
LAYER ME2 ;
ENCLOSURE 0.08 0.08 ;
LAYER VI1 ;
RECT -0.14 -0.14 0.14 0.14 ;
SPACING 0.56 BY 0.56 ;
END M1_M2

VIARULE M1_PDIFF GENERATE
LAYER DIFF ;
ENCLOSURE 0.1 0.1 ;
LAYER ME1 ;
ENCLOSURE 0.08 0.08 ;
LAYER CONT ;
RECT -0.12 -0.12 0.12 0.12 ;
SPACING 0.5 BY 0.5 ;
END M1_PDIFF

VIARULE M1_NWEL GENERATE
LAYER DIFF ;
ENCLOSURE 0.1 0.1 ;
LAYER ME1 ;
ENCLOSURE 0.08 0.08 ;
LAYER CONT ;
RECT -0.12 -0.12 0.12 0.12 ;
SPACING 0.5 BY 0.5 ;
END M1_NWEL

VIARULE M1_NDIFF GENERATE
LAYER DIFF ;
ENCLOSURE 0.1 0.1 ;
LAYER ME1 ;
ENCLOSURE 0.08 0.08 ;
LAYER CONT ;
RECT -0.12 -0.12 0.12 0.12 ;
SPACING 0.5 BY 0.5 ;
END M1_NDIFF

VIARULE M1_POLY GENERATE DEFAULT
LAYER PO1 ;
ENCLOSURE 0.1 0.1 ;
LAYER ME1 ;
ENCLOSURE 0.08 0.08 ;
LAYER CONT ;
RECT -0.12 -0.12 0.12 0.12 ;
SPACING 0.5 BY 0.5 ;
END M1_POLY

SITE CoreSite
CLASS CORE ;
SIZE 0.56 BY 124.4 ;
END CoreSite

MACRO pseudo_nmos1
CLASS BLOCK ;
ORIGIN 0.0 0.0 ;
FOREIGN pseudo_nmos1 0.0 0.0 ;
SIZE 102.5 BY 124.4 ;
SYMMETRY X Y ;
SITE CoreSite ;
PIN gnd
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER VI1 ;
RECT 0.56 -0.04 0.84 0.24 ;
RECT 2.86 -0.04 3.14 0.24 ;
RECT 2.96 88.06 3.24 88.34 ;
RECT 4.16 6.06 4.44 6.34 ;
RECT 6.46 31.26 6.74 31.54 ;
RECT 6.56 6.66 6.84 6.94 ;
RECT 6.56 -0.04 6.84 0.24 ;
RECT 6.66 53.96 6.94 54.24 ;
RECT 7.76 -0.04 8.04 0.24 ;
RECT 10.46 -0.04 10.74 0.24 ;
RECT 11.96 5.46 12.24 5.74 ;
RECT 16.36 -0.04 16.64 0.24 ;
RECT 17.56 5.86 17.84 6.14 ;
RECT 21.86 -0.04 22.14 0.24 ;
RECT 23.26 5.86 23.54 6.14 ;
LAYER ME1 ;
RECT 0 0 80.5 0.24 ;
RECT 36.1 60.5 36.5 60.9 ;
RECT 36.18 0 36.42 60.9 ;
RECT 33.73 60.25 34.13 65.08 ;
RECT 33.88 0 34.12 65.08 ;
RECT 21.78 -0.12 22.22 0.32 ;
RECT 16.28 -0.12 16.72 0.32 ;
RECT 10.38 -0.12 10.82 0.32 ;
RECT 7.68 -0.12 8.12 0.32 ;
RECT 6.48 -0.12 6.92 0.32 ;
RECT 2.78 -0.12 3.22 0.32 ;
RECT 0.48 -0.12 0.92 0.32 ;
RECT 23.23 5.74 23.63 25.18 ;
RECT 23.18 5.78 23.63 6.22 ;
RECT 17.53 5.74 17.93 25.18 ;
RECT 17.48 5.78 17.93 6.22 ;
RECT 11.93 5.34 12.33 24.78 ;
RECT 11.88 5.38 12.33 5.82 ;
RECT 6.58 53.88 7.02 54.32 ;
RECT 6.48 6.58 6.92 7.02 ;
RECT 6.38 31.18 6.82 31.62 ;
RECT 4.13 5.94 4.53 25.38 ;
RECT 4.08 5.98 4.53 6.42 ;
RECT 2.88 87.98 3.32 88.42 ;
LAYER ME2 ;
RECT 23.18 5.78 23.62 6.22 ;
RECT 21.86 5.86 23.62 6.14 ;
RECT 21.78 -0.12 22.22 0.32 ;
RECT 21.86 -0.12 22.14 6.14 ;
RECT 17.48 5.78 17.92 6.22 ;
RECT 16.36 5.86 17.92 6.14 ;
RECT 16.28 -0.12 16.72 0.32 ;
RECT 16.36 -0.12 16.64 6.14 ;
RECT 11.88 5.38 12.32 5.82 ;
RECT 10.46 5.36 12.1 5.64 ;
RECT 10.38 -0.12 10.82 0.32 ;
RECT 10.46 -0.12 10.74 5.64 ;
RECT 7.68 -0.12 8.12 0.32 ;
RECT 6.58 53.96 8.04 54.24 ;
RECT 7.76 -0.12 8.04 54.24 ;
RECT 6.38 31.26 8.04 31.54 ;
RECT 6.58 53.88 7.02 54.32 ;
RECT 6.38 31.18 6.82 31.62 ;
RECT 6.48 6.58 6.92 7.02 ;
RECT 6.48 -0.12 6.92 0.32 ;
RECT 6.56 -0.12 6.84 7.02 ;
RECT 4.08 5.98 4.52 6.42 ;
RECT 2.86 6.06 4.52 6.34 ;
RECT 2.78 -0.12 3.22 0.32 ;
RECT 2.86 -0.12 3.14 6.34 ;
RECT 2.88 87.98 3.32 88.42 ;
RECT 0.56 88.06 3.32 88.34 ;
RECT 0.48 -0.12 0.92 0.32 ;
RECT 0.56 -0.12 0.84 88.34 ;
END
END gnd
PIN c1
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 4.56 73.6 4.84 75.02 ;
RECT 4.5 73.6 4.9 74 ;
RECT 12.08 73.7 12.32 75.02 ;
RECT 0.2 74.78 12.32 75.02 ;
RECT 12 73.7 12.4 74.1 ;
END
END c1
PIN D4
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0 1.8 23.92 2.04 ;
RECT 23.68 1.8 23.92 5.2 ;
RECT 23.6 4.8 24 5.2 ;
END
END D4
PIN c4
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 4.78 26.78 5.02 27.7 ;
RECT 4.7 27.3 5.1 27.7 ;
RECT 0.3 26.78 23.82 27.02 ;
RECT 23.58 26.78 23.82 27.9 ;
RECT 23.5 27.5 23.9 27.9 ;
END
END c4
PIN c3
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0 51.2 12.52 51.44 ;
RECT 17.98 48.7 18.22 51.44 ;
RECT 12.2 51.18 18.22 51.42 ;
RECT 17.9 48.7 18.3 49.1 ;
RECT 17.98 51.2 23.32 51.44 ;
RECT 23.08 51.2 23.32 52.8 ;
RECT 23 52.4 23.4 52.8 ;
END
END c3
PIN D3
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0 2.7 18.22 2.94 ;
RECT 17.98 2.7 18.22 5.2 ;
RECT 17.9 4.8 18.3 5.2 ;
END
END D3
PIN c2
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER VI1 ;
RECT 12.26 49.06 12.54 49.34 ;
RECT 17.36 52.56 17.64 52.84 ;
LAYER VI2 ;
RECT 17.36 52.56 17.64 52.84 ;
RECT 12.26 49.06 12.54 49.34 ;
LAYER ME1 ;
RECT 17.28 52.48 17.72 52.92 ;
RECT 12.18 48.98 12.62 49.42 ;
RECT 12.2 48.3 12.6 48.7 ;
RECT 12.28 48.3 12.52 49.42 ;
RECT 0 49.1 12.62 49.34 ;
LAYER ME2 ;
RECT 17.28 52.48 17.72 52.92 ;
RECT 12.18 48.98 12.62 49.42 ;
LAYER ME3 ;
RECT 17.28 52.48 17.72 52.92 ;
RECT 12.26 52.56 17.72 52.84 ;
RECT 12.18 48.98 12.62 49.42 ;
RECT 12.26 48.98 12.54 52.84 ;
END
END c2
PIN D2
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0 3.5 12.62 3.74 ;
RECT 12.38 3.5 12.62 4.8 ;
RECT 12.3 4.4 12.7 4.8 ;
END
END D2
PIN D1
DIRECTION INOUT ;
USE SIGNAL ;
PORT
LAYER ME1 ;
RECT 0 4.5 4.82 4.74 ;
RECT 4.58 4.5 4.82 5.4 ;
RECT 4.5 5 4.9 5.4 ;
END
END D1
PIN vdd
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER ME1 ;
RECT 4.18 88.38 4.42 110.4 ;
RECT 4.1 93 4.5 93.4 ;
RECT 4.13 88.38 4.53 91.58 ;
RECT 33.58 75.32 33.82 110.4 ;
RECT 33.5 91.1 33.9 91.5 ;
RECT 33.53 75.32 33.93 89.88 ;
RECT 0 110.16 80.5 110.4 ;
END
END vdd
PIN vout
DIRECTION OUTPUT ;
USE SIGNAL ;
PORT
LAYER VI1 ;
RECT 34.32 75.4 34.6 75.68 ;
RECT 34.56 64.56 34.84 64.84 ;
RECT 35.46 70.66 35.74 70.94 ;
LAYER ME1 ;
RECT 35.38 70.68 41.9 70.92 ;
RECT 35.38 70.58 35.82 71.02 ;
RECT 34.45 64.48 34.92 64.92 ;
RECT 34.45 60.25 34.85 65.08 ;
RECT 34.24 75.32 34.68 75.76 ;
RECT 34.25 75.32 34.65 89.88 ;
LAYER ME2 ;
RECT 35.38 70.58 35.82 71.02 ;
RECT 34.24 75.41 35.76 75.69 ;
RECT 35.48 70.58 35.76 75.69 ;
RECT 35.46 64.56 35.74 71.02 ;
RECT 34.48 64.56 35.74 64.84 ;
RECT 34.48 64.48 34.92 64.92 ;
RECT 34.24 75.32 34.68 75.76 ;
END
END vout
OBS
LAYER ME1 ;
RECT 2.88 87.98 3.32 88.42 ;
RECT 4.08 53.68 4.53 54.12 ;
RECT 4.13 53.64 4.53 73.08 ;
RECT 4.08 5.98 4.53 6.42 ;
RECT 4.13 5.94 4.53 25.38 ;
RECT 4.33 28.24 4.73 47.68 ;
RECT 4.28 47.28 4.72 47.72 ;
RECT 0 4.5 4.82 4.74 ;
RECT 4.58 4.5 4.82 5.4 ;
RECT 4.5 5 4.9 5.4 ;
RECT 4.85 88.48 5.32 88.92 ;
RECT 4.85 88.38 5.25 91.58 ;
RECT 4.85 53.64 5.25 73.08 ;
RECT 4.88 72.68 5.32 73.12 ;
RECT 4.85 5.94 5.25 25.38 ;
RECT 4.88 24.98 5.32 25.42 ;
RECT 5.05 28.28 5.52 28.72 ;
RECT 5.05 28.24 5.45 47.68 ;
RECT 6.38 31.18 6.82 31.62 ;
RECT 6.48 6.58 6.92 7.02 ;
RECT 6.58 53.88 7.02 54.32 ;
RECT 11.58 53.78 12.03 54.22 ;
RECT 11.63 53.74 12.03 73.18 ;
RECT 11.83 28.34 12.23 47.78 ;
RECT 11.78 47.38 12.22 47.82 ;
RECT 11.88 5.38 12.33 5.82 ;
RECT 11.93 5.34 12.33 24.78 ;
RECT 4.5 73.6 4.9 74 ;
RECT 12 73.7 12.4 74.1 ;
RECT 4.56 73.6 4.84 75.02 ;
RECT 12.08 73.7 12.32 75.02 ;
RECT 0.2 74.78 12.32 75.02 ;
RECT 12.2 48.3 12.6 48.7 ;
RECT 12.28 48.3 12.52 49.42 ;
RECT 0 49.1 12.62 49.34 ;
RECT 12.18 48.98 12.62 49.42 ;
RECT 0 3.5 12.62 3.74 ;
RECT 12.38 3.5 12.62 4.8 ;
RECT 12.3 4.4 12.7 4.8 ;
RECT 12.55 28.38 13.02 28.82 ;
RECT 12.55 28.34 12.95 47.78 ;
RECT 12.58 24.28 13.05 24.72 ;
RECT 12.65 5.34 13.05 24.78 ;
RECT 16.88 53.48 17.33 53.92 ;
RECT 16.93 53.44 17.33 72.88 ;
RECT 17.28 52.48 17.72 52.92 ;
RECT 17.48 47.68 17.93 48.12 ;
RECT 17.53 28.74 17.93 48.18 ;
RECT 17.48 5.78 17.93 6.22 ;
RECT 17.53 5.74 17.93 25.18 ;
RECT 0 2.7 18.22 2.94 ;
RECT 17.98 2.7 18.22 5.2 ;
RECT 17.9 4.8 18.3 5.2 ;
RECT 18.25 28.78 18.72 29.22 ;
RECT 18.25 28.74 18.65 48.18 ;
RECT 18.25 5.74 18.65 25.18 ;
RECT 18.28 24.78 18.72 25.22 ;
RECT 22.58 53.38 23.03 53.82 ;
RECT 22.63 53.34 23.03 72.78 ;
RECT 17.9 48.7 18.3 49.1 ;
RECT 17.98 48.7 18.22 51.44 ;
RECT 12.2 51.18 18.22 51.42 ;
RECT 0 51.2 12.52 51.44 ;
RECT 17.98 51.2 23.32 51.44 ;
RECT 23.08 51.2 23.32 52.8 ;
RECT 23 52.4 23.4 52.8 ;
RECT 23.13 28.44 23.53 47.88 ;
RECT 23.08 47.48 23.52 47.92 ;
RECT 23.18 5.78 23.63 6.22 ;
RECT 23.23 5.74 23.63 25.18 ;
RECT 0.3 26.78 23.82 27.02 ;
RECT 4.78 26.78 5.02 27.7 ;
RECT 23.58 26.78 23.82 27.9 ;
RECT 4.7 27.3 5.1 27.7 ;
RECT 23.5 27.5 23.9 27.9 ;
RECT 0 1.8 23.92 2.04 ;
RECT 23.68 1.8 23.92 5.2 ;
RECT 23.6 4.8 24 5.2 ;
RECT 23.95 5.74 24.35 25.18 ;
RECT 24.15 24.98 25.5 25.38 ;
RECT 25.1 24.98 25.5 29 ;
RECT 23.85 28.6 25.5 29 ;
RECT 23.85 28.44 24.25 47.88 ;
RECT 34.1 65.9 34.5 66.3 ;
RECT 34.2 65.9 34.44 69.74 ;
RECT 31.39 69.5 34.44 69.74 ;
RECT 31.39 69.5 31.63 72.53 ;
RECT 23.35 72.38 28.12 72.62 ;
RECT 23.35 53.34 23.75 72.78 ;
RECT 17.65 53.44 18.05 72.88 ;
RECT 31.38 72.22 31.62 73.13 ;
RECT 12.35 72.88 13.82 73.12 ;
RECT 27.88 72.89 31.62 73.13 ;
RECT 12.35 53.74 12.75 73.18 ;
RECT 27.88 73.59 34.21 73.83 ;
RECT 33.97 73.59 34.21 74.8 ;
RECT 33.9 74.4 34.3 74.8 ;
RECT 13.58 72.88 13.82 81.52 ;
RECT 17.78 53.44 18.02 81.52 ;
RECT 27.88 72.38 28.12 81.52 ;
RECT 5.78 81.28 28.12 81.52 ;
RECT 5.78 81.18 6.22 81.62 ;
RECT 34.24 75.32 34.68 75.76 ;
RECT 34.25 75.32 34.65 89.88 ;
RECT 34.45 64.48 34.92 64.92 ;
RECT 34.45 60.25 34.85 65.08 ;
RECT 35.38 70.68 41.9 70.92 ;
RECT 35.38 70.58 35.82 71.02 ;
RECT 33.53 75.32 33.93 89.88 ;
RECT 33.5 91.1 33.9 91.5 ;
RECT 4.13 88.38 4.53 91.58 ;
RECT 4.1 93 4.5 93.4 ;
RECT 4.18 88.38 4.42 110.4 ;
RECT 33.58 75.32 33.82 110.4 ;
RECT 0 110.16 80.5 110.4 ;
RECT 0 0 80.5 0.24 ;
RECT 0.48 -0.12 0.92 0.32 ;
RECT 2.78 -0.12 3.22 0.32 ;
RECT 6.48 -0.12 6.92 0.32 ;
RECT 7.68 -0.12 8.12 0.32 ;
RECT 10.38 -0.12 10.82 0.32 ;
RECT 16.28 -0.12 16.72 0.32 ;
RECT 21.78 -0.12 22.22 0.32 ;
RECT 33.88 0 34.12 65.08 ;
RECT 36.18 0 36.42 60.9 ;
RECT 36.1 60.5 36.5 60.9 ;
RECT 33.73 60.25 34.13 65.08 ;
LAYER VI1 ;
RECT 0.56 -0.04 0.84 0.24 ;
RECT 2.86 -0.04 3.14 0.24 ;
RECT 2.96 88.06 3.24 88.34 ;
RECT 4.16 53.76 4.44 54.04 ;
RECT 4.16 6.06 4.44 6.34 ;
RECT 4.36 47.36 4.64 47.64 ;
RECT 4.96 88.56 5.24 88.84 ;
RECT 4.96 72.76 5.24 73.04 ;
RECT 4.96 25.06 5.24 25.34 ;
RECT 5.16 28.36 5.44 28.64 ;
RECT 5.86 81.26 6.14 81.54 ;
RECT 6.46 31.26 6.74 31.54 ;
RECT 6.56 6.66 6.84 6.94 ;
RECT 6.56 -0.04 6.84 0.24 ;
RECT 6.66 53.96 6.94 54.24 ;
RECT 7.76 -0.04 8.04 0.24 ;
RECT 10.46 -0.04 10.74 0.24 ;
RECT 11.66 53.86 11.94 54.14 ;
RECT 11.86 47.46 12.14 47.74 ;
RECT 11.96 5.46 12.24 5.74 ;
RECT 12.26 49.06 12.54 49.34 ;
RECT 12.66 28.46 12.94 28.74 ;
RECT 12.66 24.36 12.94 24.64 ;
RECT 16.36 -0.04 16.64 0.24 ;
RECT 16.96 53.56 17.24 53.84 ;
RECT 17.36 52.56 17.64 52.84 ;
RECT 17.56 47.76 17.84 48.04 ;
RECT 17.56 5.86 17.84 6.14 ;
RECT 18.36 28.86 18.64 29.14 ;
RECT 18.36 24.86 18.64 25.14 ;
RECT 21.86 -0.04 22.14 0.24 ;
RECT 22.66 53.46 22.94 53.74 ;
RECT 23.16 47.56 23.44 47.84 ;
RECT 23.26 5.86 23.54 6.14 ;
RECT 34.32 75.4 34.6 75.68 ;
RECT 34.56 64.56 34.84 64.84 ;
RECT 35.46 70.66 35.74 70.94 ;
LAYER ME2 ;
RECT 0.48 -0.12 0.92 0.32 ;
RECT 0.56 -0.12 0.84 88.34 ;
RECT 0.56 88.06 3.32 88.34 ;
RECT 2.88 87.98 3.32 88.42 ;
RECT 2.78 -0.12 3.22 0.32 ;
RECT 2.86 -0.12 3.14 6.34 ;
RECT 2.86 6.06 4.52 6.34 ;
RECT 4.08 5.98 4.52 6.42 ;
RECT 3.26 47.36 4.72 47.64 ;
RECT 4.28 47.28 4.72 47.72 ;
RECT 3.26 47.36 3.54 54.04 ;
RECT 3.26 53.76 4.52 54.04 ;
RECT 4.08 53.68 4.52 54.12 ;
RECT 4.88 72.76 6.14 73.04 ;
RECT 4.88 72.68 5.32 73.12 ;
RECT 5.78 81.18 6.22 81.62 ;
RECT 5.86 72.76 6.14 88.84 ;
RECT 4.88 88.56 6.14 88.84 ;
RECT 4.88 88.48 5.32 88.92 ;
RECT 4.88 25.06 6.64 25.34 ;
RECT 4.88 24.98 5.32 25.42 ;
RECT 6.36 25.06 6.64 28.64 ;
RECT 5.08 28.36 6.64 28.64 ;
RECT 5.08 28.28 5.52 28.72 ;
RECT 6.48 -0.12 6.92 0.32 ;
RECT 6.56 -0.12 6.84 7.02 ;
RECT 6.48 6.58 6.92 7.02 ;
RECT 7.68 -0.12 8.12 0.32 ;
RECT 6.38 31.26 8.04 31.54 ;
RECT 6.38 31.18 6.82 31.62 ;
RECT 7.76 -0.12 8.04 54.24 ;
RECT 6.58 53.96 8.04 54.24 ;
RECT 6.58 53.88 7.02 54.32 ;
RECT 10.06 47.46 12.22 47.74 ;
RECT 11.78 47.38 12.22 47.82 ;
RECT 10.06 47.46 10.34 54.14 ;
RECT 10.06 53.86 12.02 54.14 ;
RECT 11.58 53.78 12.02 54.22 ;
RECT 10.38 -0.12 10.82 0.32 ;
RECT 10.46 -0.12 10.74 5.64 ;
RECT 10.46 5.36 12.1 5.64 ;
RECT 11.88 5.38 12.32 5.82 ;
RECT 12.18 48.98 12.62 49.42 ;
RECT 12.58 24.36 14.24 24.64 ;
RECT 12.58 24.28 13.02 24.72 ;
RECT 13.96 24.36 14.24 28.74 ;
RECT 12.58 28.46 14.24 28.74 ;
RECT 12.58 28.38 13.02 28.82 ;
RECT 17.28 52.48 17.72 52.92 ;
RECT 15.86 47.76 17.92 48.04 ;
RECT 17.48 47.68 17.92 48.12 ;
RECT 15.86 47.76 16.14 53.84 ;
RECT 15.86 53.56 17.32 53.84 ;
RECT 16.88 53.48 17.32 53.92 ;
RECT 16.28 -0.12 16.72 0.32 ;
RECT 16.36 -0.12 16.64 6.14 ;
RECT 16.36 5.86 17.92 6.14 ;
RECT 17.48 5.78 17.92 6.22 ;
RECT 18.28 24.86 19.94 25.14 ;
RECT 18.28 24.78 18.72 25.22 ;
RECT 19.66 24.86 19.94 29.14 ;
RECT 18.28 28.86 19.94 29.14 ;
RECT 18.28 28.78 18.72 29.22 ;
RECT 21.56 47.56 23.52 47.84 ;
RECT 23.08 47.48 23.52 47.92 ;
RECT 21.56 47.56 21.84 53.74 ;
RECT 21.56 53.46 23.02 53.74 ;
RECT 22.58 53.38 23.02 53.82 ;
RECT 21.78 -0.12 22.22 0.32 ;
RECT 21.86 -0.12 22.14 6.14 ;
RECT 21.86 5.86 23.62 6.14 ;
RECT 23.18 5.78 23.62 6.22 ;
RECT 34.48 64.56 35.74 64.84 ;
RECT 34.48 64.48 34.92 64.92 ;
RECT 35.46 64.56 35.74 71.02 ;
RECT 35.38 70.58 35.82 71.02 ;
RECT 35.48 70.58 35.76 75.69 ;
RECT 34.24 75.41 35.76 75.69 ;
RECT 34.24 75.32 34.68 75.76 ;
LAYER VI2 ;
RECT 12.26 49.06 12.54 49.34 ;
RECT 17.36 52.56 17.64 52.84 ;
LAYER ME3 ;
RECT 12.18 48.98 12.62 49.42 ;
RECT 12.26 48.98 12.54 52.84 ;
RECT 12.26 52.56 17.72 52.84 ;
RECT 17.28 52.48 17.72 52.92 ;
END
PROPERTY oaTaper "__DerivedDefaultTaperCG" ;
END pseudo_nmos1

END LIBRARY


********Encounter Log , It has only warnings****************************

encounter 1> *** Memory pool thread-safe mode activated.

Loading Lef file ../../Desktop/a/a_test.lef...
**WARN: (ENCLF-122): The direction of the layer 'ME1' is the same as
the previous routing layer. Make sure this is on purpose or correct
the direction of the layer. In most cases, the routing layers
alternate in direction between HORIZONTAL and VERTICAL.
**WARN: (ENCLF-155): ViaRule only supports routing/cut layer, but poly layer found for viaRule 'M1_PDIFF',
**WARN: (ENCLF-155): ViaRule only supports routing/cut layer, but poly layer found for viaRule 'M1_NWEL',
**WARN: (ENCLF-155): ViaRule only supports routing/cut layer, but poly layer found for viaRule 'M1_NDIFF',
Set DBUPerIGU to M2 pitch 480.

Power Planner/ViaGen version 8.1.46 promoted on 02/17/2009.
viaInitial starts at Tue Oct 22 12:39:35 2013
**WARN: (ENCPP-546): The power planner will ignore via rule 'M1_PDIFF' because the via rule contains geometry mismatches.
**WARN: (ENCPP-546): The power planner will ignore via rule 'M1_NWEL' because the via rule contains geometry mismatches.
**WARN: (ENCPP-546): The power planner will ignore via rule 'M1_NDIFF' because the via rule contains geometry mismatches.
viaInitial ends at Tue Oct 22 12:39:35 2013
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist '../../Desktop/tmp.v'

*** Memory Usage v#188 (Current mem = 214.730M, initial mem = 45.809M) ***
*** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=214.7M) ***
Top level cell is tmp.
*** End library_loading (cpu=0.00min, mem=0.0M, fe_cpu=0.04min, fe_mem=214.7M) ***
Starting recursive module instantiation check.
No recursion found.
Building hierarchical netlist for Cell tmp ...
*** Netlist is unique.
Set DBUPerIGU to techSite CoreSite width 560.
Setting Std. cell height to 124400 DBU, based on Site CoreSite.
**WARN: (ENCTRN-1101): Could not determine power-rail locations in cells, using GNDOnBtm
**WARN: (ENCTRN-1102): Could not determine power-rail locations of some cells.
Forcing all single height cell pwr-rail setting to GND-on-bottom.
** info: there are 2 modules.
** info: there are 0 stdCell insts.
** info: there are 1 macros.

*** Memory Usage v#188 (Current mem = 216.738M, initial mem = 45.809M) ***
**WARN: (ENCRM-128): Total 1 bad sites (size is not multiple of H/V pitch).
Horizontal Layer M2 offset = 240 (guessed)
Vertical Layer M3 offset = 280 (derived)
Suggestion: specify LAYER OFFSET in LEF file
Reason: hard to extract LAYER OFFSET from standard cells
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
Set Input Pin Transition Delay as 0.1 ps.
**WARN: (ENCSYT-7328): Active setup and hold analysis views were not provided by the -setup and -hold arguments to initDesign. The system requires at least one active setup and hold analysis view to be declared before any timing commands can be run. If you need to run timing commands, you can add the -setup and -hold options to your init_design invocation. You can use the all_analysis_view command to identify the currently available views.






Thanks

 

[rca]

Re: Writing out .lib & lef from virtuoso

well where is your problem, now?

 

[wipshami]

Re: Writing out .lib & lef from virtuoso

The problem is that the encounter shows only a rectangle with orientation with no selectivity . So I am not able to place this inside a floorplan

 

[rca]

Re: Writing out .lib & lef from virtuoso

are you able to place it via command PlaceInstance...?

for non rectangle shape, you need to have the OVERLAP layer define in your techno lef file.

LAYER OVERLAP
    TYPE OVERLAP ;
END OVERLAP

 

[vimalraj205]

Re: Writing out .lib & lef from virtuoso

hai
selectivity is not the problem of lef its something with your tool .
In the layer control have you enbled the Block selectivity Checkbox .
please check this

 

[wipshami]

Re: Writing out .lib & lef from virtuoso

the shape is rectangular and I have enabled the block selectivity in check box also. still its not resolved

Instead of loading lef , can i load OA to encounter and do IO planning for the block? Is it having the same effect as loading lef ?

Thanks

 

[vimalraj205]

Re: Writing out .lib & lef from virtuoso

hai friend

i have loaded your lef and i have placed your block inside the core and i have attached the screenshot of it

i am confused why you are not able to do it



thank you

 

[wipshami]

Re: Writing out .lib & lef from virtuoso

Hi Thanks

Now I can also do that . As you said above it was not issue with the lef , tool showed me the block only with command PlaceInst* . Thanks for the friend who suggested the command:-o

Issue fixed..Thanks for all helps:grin:

- - - Updated - - -