how can i write matrix in verilog

[boldmaa]

hi guys. please help me. how can i write matrix function, and multiplication, divide, munis, plus etc arithmetic operation between the matrices in verilog.
please contact me. thank you.

 

[nikhilna007]

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Code Verilog - [expand]
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reg [7:0]a;

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'a' is a array having 8 bits.

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Code Verilog - [expand]
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reg [7:0]b[100];

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'b' is one dimensional array having 100 elements with each element having 8 bits

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Code Verilog - [expand]
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reg [7:0]c[100][100];

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'c' is a two dimensional array of size [100][100] and each element having 8 bits.



you can use for loop for doing matrix addition,minus ,plus etc..

 

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you can use for loop for doing matrix addition,minus ,plus etc..

You'll probably make this kind of mistake if you "think" like a software programmer. Doing this will result in every multiplication and addition being implemented in hardware, after the for loop is unrolled.

Unless you need that kind of performance (e.g. heavily pipelined design with outputs on every clock cycle) you'll probably want to share resources and reduce the number of multipliers required by time-division-multiple-access of the multiplier, using an FSM to control the calculations.

Regards

 

[nikhilna007]

i am taking a lot of time to synthesize my code .
is it because of the use of for loop.

regards

 

[boldmaa]

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Code Verilog - [expand]
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reg [7:0] x0[1:2][1:1];// matrix value save in register. x0 is matrix; [1:2]- row number; [1:1]-column number;
x0[1][1] = 0; // x0 matrix a11=0;
x0[2][1] = 0; //x0 matrix a21=0;

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i think that but x0[1][1] = 0; is wrong in Active HDL 7.2 student edition

 

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reg [7:0] x0[1:2][1:1];// matrix value save in register. x0 is matrix; [1:2]- row number; [1:1]-column number;
x0[1][1] = 0; // x0 matrix a11=0;
x0[2][1] = 0; //x0 matrix a21=0;
i think that but x0[1][1] = 0; is wrong in Active HDL 7.2 student edition

If x0[1][1] = 0; // x0 matrix a11=0; is actually what you have described in your file then...
You've incorrectly assigned the value to x0[1][1] if it's not in a combinational always block.

Do either of these:

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Code Verilog - [expand]
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// use a combination always block
always @* begin
  x0[1][1] = 0; // x0 matrix a11=0;
  x0[2][1] = 0; //x0 matrix a21=0;
end
 
// use an assign
assign x0[1][1] = 0; // x0 matrix a11=0;
assign x0[2][1] = 0; //x0 matrix a21=0;

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I believe there is a small performance gain using the always block as opposed to the assign, but I've seen some papers that suggest the gain isn't all that significant.

Regards

 

[kommu4946]

You'll probably make this kind of mistake if you "think" like a software programmer. Doing this will result in every multiplication and addition being implemented in hardware, after the for loop is unrolled.

Unless you need that kind of performance (e.g. heavily pipelined design with outputs on every clock cycle) you'll probably want to share resources and reduce the number of multipliers required by time-division-multiple-access of the multiplier, using an FSM to control the calculations.

But using FSM we need to wait for certain number of clock cycles (depending up on fsm) to get final multiplied values. In order to avoid wastage of clock cycles ,Can i use one more clock faster than design clock so that fsm is controlled using faster clock to get values in one design clock ?

 

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But using FSM we need to wait for certain number of clock cycles (depending up on fsm) to get final multiplied values. In order to avoid wastage of clock cycles ,Can i use one more clock faster than design clock so that fsm is controlled using faster clock to get values in one design clock ?

This is design dependent and can only be determined with knowledge of the clock frequencies involved and the technology node being used.

e.g. System clock is 10 MHz with a 10 pipeline stage multiplier at 100 MHz is doable. A system clock of 100 MHz, with the same 10 pipeline stage multiplier is not doable in an FPGA.

If you're running with a low system clock frequency then it's not likely you'll need to pipeline anything, with the latest generation of FPGAs.

Regards