Re: How can i write testbench and monitor all the AXI4 bus signals in vivado ??
SDK is only a platform for you to generate an ELF file from your C code.
Imagine the ELF file as instructions for the uBlaze to do something which will reside inside the FPGA BRAM/s. In the test bench when you provide continuous clk and after reset, the uBlaze reads those instructions from the BRAM/s and does something. For your case, this something will be either sending out the "Hello World" message via AXI UART or writing something to a DDR3. In both cases, a bus-transaction is generated by the uBlaze. This transaction you can see in simulation.
Using a uBlaze just makes your life easy, having not to write a real test-bench.
If you want to write a "real" test bench, I you need to change your h/w design a bit, i,e the DUT. There are many options, but I will not elaborate on it here.
Hope I am clear!