but the low divide frequency for sram is difficult to synchronize the 40MHZ clk,example 15ns skew will make sram store error data.
bitscope also use TLC5540 for DSO ADC,he is how to realize it?
from the PCB picture(no more Clear picture),he maybe use a clock synthesizer chip for it,but I don't known what's chip from the picture?
this is my dso block picture.
clk1 is 40MHZ for ADC and sram,CLK2 is low freuqency clock,and is divided from CLK1.
CLK1:10KHZ-40MHZ
my question:
when CLK1=40MHZ and CLK2=40MHZ,because of divide and multiplexer circuit delay,so skew is very large between CLK1 and CLK2, this large skew will make sram store error data.