How can i use TLC5540 for low sample rate in DSO?

[alphi]

tlc5540

I wang use TLC5540 for my DSO project,but TLC5540 min sample rate is 5MHZ,if I want several KHZ sample rate,how can I do it?

 

[IanP]

tlc5540 pic

The maximum clock frequency is 40MHz ..
For slower operation use slower clock .. and don't worry much about "Minimum Coversion Rate" TYP 5 MSPS ..

Regards,
IanP

 

[budhy]

tlc5540*pcb

Minimum conversion rate of TLC5540 is 5 MHz, you can't use lower clock, but you can collect the conversion result at slower rate as you want.

 

[IanP]

sample dso presentation

I think you can go with the frequency of the CLOCK signal as low as you like .. see attached picture ..

Regards,
IanP

 

[alphi]

tlc5540 adc circuit pcb

budhy,how can I collect data with low rate? I can use 40MHZ or 5MHZ for ADC(TLC5540),but I can't generate a low frequency sram address signal.


TLC5540 can not work with lowwer sample rate,or the sample result will be error.

 

[Giuss]

tlc5540 minimum sample rate

I'we used a fixed frequency of 40 Mhz for the ADC and a frequency divider for the RAM sampling

 

[alphi]

tlc5540 example

but the low divide frequency for sram is difficult to synchronize the 40MHZ clk,example 15ns skew will make sram store error data.

bitscope also use TLC5540 for DSO ADC,he is how to realize it?
from the PCB picture(no more Clear picture),he maybe use a clock synthesizer chip for it,but I don't known what's chip from the picture?

 

[budhy]

dso sram

From the Terminal Function on data sheet page 3:

OE (pin 1) - Output enable. When OE = L, data is enabled. When OE = H, D1−D8 is high impedance.

you can control OE asynchronously at any rate ro collect data from TLC5540

 

[alphi]

only control OE is not realize lower sample. the sram also need lower frequecy address bus.

 

[Giuss]

In my design i've used a CPLD and I've no problems of synchronization

 

[alphi]

Giuss,can you give me a detail method for it?

my email:alphifly@gmail.com

 

[alphi]

this is my dso block picture.
clk1 is 40MHZ for ADC and sram,CLK2 is low freuqency clock,and is divided from CLK1.
CLK1:10KHZ-40MHZ

my question:
when CLK1=40MHZ and CLK2=40MHZ,because of divide and multiplexer circuit delay,so skew is very large between CLK1 and CLK2, this large skew will make sram store error data.

how can i do with it?