i am trying to do a simulation with a pre-CTS sdf, so i am forced to hack the clock tree cell delay and interconnect delay to 0, but it will cause hold timing violation on DFF, so, how can i turn off "hold" timing check in ncverilog? i know, i can make sdf annotator ignore hold time annotation, but the verilog library still has that specify...
Yes, notimingcheck can solve this issue, but it is a global option and it will turn off setup/recoveray/removal too, i just want to turn off "hold" check and i am not planning to turn off all timing check
HolySaint said:
IF U USE VCS ,U CAN ADD THE +notimingcheck to turn off it