How can I test my own FPGA board design with PowerPc?

[ghostt]

Hello

I have Fpga design which is created in Modelsim. I want to see that whether it is working properly with PowerPc or not before fabricating it. which way do I need to follow to integrate Power Pc in my specific design and see output without board? i also want to run my C/C++ code on my ppc that might be communicate some peripherals.

I couldn' t find any case study about the simulation of Power Pc? anybody suggest me a way to solve it?

Thank you.

 

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You created the design in Modelsim? Modelsim is a simulator not a design creation tool.

To see if your FPGA design works with a PPC then get/write a bus functional model (BFM) of the PPC bus your connecting to the FPGA and write a testbench with both the UUT (FPGA) and the BFM. Use the BFM to test if your FPGA works.

i also want to run my C/C++ code on my ppc that might be communicate some peripherals.

why? If you talking about communicating with the FPGA then a BFM will suffice you don't need C/C++ code running on a PPC behavioral model (which you'll never find).
If you're trying to do board level simulations then you're going about this the wrong way. Modelsim isn't a board level simulator.

-alan

 

[ghostt]

thanks alan that is what i am looking for, could you suggest me good reference to write BFM?



morever, i want to create file system top level of my design that is why i want to run C/C++ in my board. what would u suggest me?

 

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the reference is the PPC datasheet and time ;-) That's how I've always written BFMs for parts that don't have a model that I could download.

as to the structure of a BFM...some bus transactor code that is cycle accurate and adheres to the protocol (and checks that it's not violated) along with a bunch of tasks that you can use as calls in a testcase that perform writes/reads/read_compares etc.

morever, i want to create file system top level of my design that is why i want to run C/C++ in my board. what would u suggest me?

Personally I've never worked with a mixed HW & SW (C/C++) co-simulation environment. Usually a board is designed with the FPGA and the processor and the board is built and is powered up. Any debug to get the processor and FPGA functioning is done and that is the development platform for the SW types.

-alan