How can i solve that that error?

[tryingsth]

Error: Can't place 514 pins with 2.5 V I/O standard because Fitter has only 342 such free pins available for general purpose I/O placement

 

[ads_ee]

use a part with more user I/O.

or give more details on why you are trying to shoe horn 514 pins into a part with 342 user I/O pins.

 

[tryingsth]

sorry i didn't give more information. I'm using Cyclone3 EP3C16F484C6N FPGA. when I change I/O voltages sth are changing but this didn't solve the problem. I couldn't understand.
I'm new at FPGA so this hard to solve. If you know could you explain simply,please?
thanks

 

[barry]

You've got a part with 484 TOTAL pins, many of which are dedicated to power, etc. Again, you can't use more pins than you have.

 

[tryingsth]

You've got a part with 484 TOTAL pins, many of which are dedicated to power, etc. Again, you can't use more pins than you have.

So, What can I do for solution? how can change number of pins or which device can i use?

 

[barry]

Is this your first FPGA design?

Maybe you should start with a simpler project...

 

[tryingsth]

Is this your first FPGA design?

Maybe you should start with a simpler project...

Yes,t his the first project and unfortunately I can't change. this is hard for me.but i must do that

 

[barry]

Well, if you can't change the number of i/o pins you need, you'll need to pick a different FPGA, right?

 

[permute]

if you have a dev board, you should never run out of io pins because you know what IO you have available and shouldn't make choices that would use other IO's.

If this is your first FPGA design, you should clarify what your goals are. In FPGA designs, the top level ports are connected to IO's, and many tools will try to auto-connect IOBs if you don't specify where they should be placed. This is actually a very bad default choice, but it is what vendors have chosen.

I suspect you have a design that you've simulated, and that had several ports. When you chose synthesis, it tried to assign these top level ports to IO pins.

Check to see how to disable IO insertion if you are just trying to see how the logic maps to the FPGA internals. If you want a practical design, select the IOs to match what is on your dev board. If you are designing a new board, you would need to move to a bigger FPGA or change your IO.

 

[tryingsth]

if you have a dev board, you should never run out of io pins because you know what IO you have available and shouldn't make choices that would use other IO's.

If this is your first FPGA design, you should clarify what your goals are. In FPGA designs, the top level ports are connected to IO's, and many tools will try to auto-connect IOBs if you don't specify where they should be placed. This is actually a very bad default choice, but it is what vendors have chosen.

I suspect you have a design that you've simulated, and that had several ports. When you chose synthesis, it tried to assign these top level ports to IO pins.

Check to see how to disable IO insertion if you are just trying to see how the logic maps to the FPGA internals. If you want a practical design, select the IOs to match what is on your dev board. If you are designing a new board, you would need to move to a bigger FPGA or change your IO.

Hello,

I changed outputs.prefering less number of output solved this. I need new something. I try to calculate runtime. But I don't know how I can do.Do you have an idea for this.

Thanks a lot for your all helps.

 

[barry]

What do you mean "calculate run time"? Do you mean operating frequency?

 

[tryingsth]

I try to make average filtering and I want to know how long my code takes time to calculate from first pixel to last pixel. I write similar code at C and I get runtime. Now I must get the runtime at vhdl to compare them. The clock value at C, i must assign this at vhdl to compare both of them. But i don't know the value.
I hope I explain the problem

 

[rberek]

Simulate your code.

r.b.

 

[barry]

FPGAs are not software, they are hardware; don't make the mistake of equating VHDL with a programming language like C. You are creating hardware, NOT SOFTWARE. I can not emphasize this enough to new FPGA users.

You can simulate if you want, but since hardware is completely deterministic you should be able to determine how long it takes to run a process if you understand your hardware. It is totally dependent on number of clock cycles and, thus, clock frequency.

 

[tryingsth]

FPGAs are not software, they are hardware; don't make the mistake of equating VHDL with a programming language like C. You are creating hardware, NOT SOFTWARE. I can not emphasize this enough to new FPGA users.

You can simulate if you want, but since hardware is completely deterministic you should be able to determine how long it takes to run a process if you understand your hardware. It is totally dependent on number of clock cycles and, thus, clock frequency.

Yes i think so.I couldn't solve this exactly. I can determine the frequency so I can determine the run time, i know. But i ask , because maybe sth can be.


Thanks for all helps

 

[barry]

I don't understand that statement "maybe sth can be".

 

[tryingsth]

I don't understand that statement "maybe sth can be".

Maybe it can be silly but I thought that if I gave a proximate value (real clock frequency) maybe I found a value. But I determine start and finish so it won't work. I think I can only show simulation and make explanation. Because of that i said "mayeb sth can be".

 

[tryingsth]

if you have a dev board, you should never run out of io pins because you know what IO you have available and shouldn't make choices that would use other IO's.

If this is your first FPGA design, you should clarify what your goals are. In FPGA designs, the top level ports are connected to IO's, and many tools will try to auto-connect IOBs if you don't specify where they should be placed. This is actually a very bad default choice, but it is what vendors have chosen.

I suspect you have a design that you've simulated, and that had several ports. When you chose synthesis, it tried to assign these top level ports to IO pins.

Check to see how to disable IO insertion if you are just trying to see how the logic maps to the FPGA internals. If you want a practical design, select the IOs to match what is on your dev board. If you are designing a new board, you would need to move to a bigger FPGA or change your IO.

I solve the error with a changing sth.I want to say maybe somebody need this. My mistake is, I use 2D integer array for output and ı didn't give a range. So compiler try to calculate negatif integer.So there are a lot of unnecessary number for pins. I arrange this 0 to 255 and the error is solved.

 

[TrickyDicky]

I suggest you dont use integers for a top level design - you need to assign the pins at some point, and integer bits are not available in code with integers.

 

[tryingsth]

Hello again,
@TrickyDicky At the beginning I assign integer value and I develop my project according this.So After this time it looks to me very hard to change the types.
I have a new problem. Finally I don't have any error while compilation and simulation. But there is no change at output values. The values aren't assigned.

What should I do?

Thanks