jacksparrow93
Newbie level 4
So i wrote this code (code is working on nexys 3) and when i'm trying to simulate it (created VHDL test brench, clicked on simulate behavioral model) it just gives me errors(syntax, illegal identifier, possible infinite loop)... How can i simulate it?
Code is:
Code is:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity glavni is
port(
start_stop, reset, cp: in STD_LOGIC;
led: out STD_LOGIC_VECTOR (6 downto 0);
anode: buffer STD_LOGIC_VECTOR(3 downto 0)
);
end glavni;
architecture Behavioral of glavni is
signal temp: std_logic_vector (7 downto 0);
signal cp_o,cp_o1: std_logic;
signal x: std_logic_vector(1 downto 0);
signal prikaz:std_logic_vector(3 downto 0);
begin
S1: entity work.FreqDivGen generic map (100000000) port map (cp, cp_o);
S2: entity work.FreqDivGen generic map (500000) port map (cp, cp_o1);
process(cp_o, reset, start_stop)
begin
if(reset = '1') then
temp <= "00111011";--3B
elsif(rising_edge(cp_o)) then
if(temp = "00000000") then
temp <= "00111011"; --3B
elsif(start_stop = '1') then
temp <= temp - 1;
else
temp <= temp;
end if;
end if;
end process;
process(cp_o1) --brojac brzine 200HZ-a
begin
if(cp_o1'event and cp_o1='1') then
x<=x+1;
end if;
end process;
process(x) -- Vremenski multiplekser, reagira na brojac koji je 200HZ i pali/gasi anode, prikaz znaka ovisi o trenutnom stanju FSM-a
begin
case x is
when "00" => anode<="1110";
when "01" => anode<="1101";
when others => anode<="1111";
end case;
end process;
process(anode)
begin
case anode is
when "1110" => prikaz<=temp(3 downto 0);
when others => prikaz<=temp(7 downto 4);
end case;
end process;
with prikaz select
led<= "0000001" when "0000", --0 (abcdefg)
"1111001" when "0001", --1
"0010010" when "0010", --2
"0000110" when "0011", --3
"1001100" when "0100", --4
"0100100" when "0101", --5
"0100000" when "0110", --6
"0001111" when "0111", --7
"0000000" when "1000", --8
"0000100" when "1001", --9
"0001000" when "1010", --a
"1100000" when "1011", --b
"0110001" when "1100", --c
"1000010" when "1101", --d
"0110000" when "1110", --e
"0111000" when others; --f
end Behavioral;
Code:
--------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------
entity FreqDivGen is
generic(nfCLK: natural := 100);
port(
clk: in STD_LOGIC := '0';
clk_o: buffer STD_LOGIC := '0'
);
end FreqDivGen;
architecture Behavioral of FreqDivGen is
begin
process(clk)
variable temp: integer range 0 to nfCLK/2 := 0;
begin
if (clk'event and clk='1') then
temp:=temp+1;
if (temp>=nfCLK/2) then
clk_o<=not clk_o;
temp:=0;
end if;
end if;
end process;
end Behavioral;