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How can I programme single gates in structure of CPLD orFPGA

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smiga

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Hello,
How can I programme single primitive gates in structure of CPLD or FPGA?
I'm useing MAX+plus II and in that environment it is impossible (if I am not wrong) I can programme only macrocells (LCELL) - propagation delay about few ns.
I'd like to assemble delay line with single gates - propagation delay of one gate about 50-100 ps (maybe less)

thanks in advance for help
Arek
 

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