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how can i make this code synthesisable?

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yushionly

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hi~
when i synthesis the code below,it tells me that "!==" is not synthesisable,how can i change it?
thanks

for (n=0; n<addr_width; n=n+1)
begin
LATCHED_A[n] = (NOT_A[n]!==LAST_NOT_A[n]) ? 1'bx : LATCHED_A[n] ;
end
 

yushionly

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when i use "!=",the result is not right, this code is a part of a memory code
 

FvM

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Do you understand the purpose of the "case inequality" operator !== in this place? It's explained this way in the Verilog standard:
a !== b a not equal to b, including x and z

Whatever it's meaning in the presented code may be, the constant 1'bx isn't synthesizable as well. Obviously, the code is only meaningful in simulation.
 

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I noticed, that the unsupported constructs list from link #1 isn't fully correct. Initial blocks are usually supported by FPGA synthesis tools to specify the power-up condition of registers.
 

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