How can I make my own ip core ?

[pahol]

ise create my own ip core from my vhdl code

Can somebody please help me ?
I have my own ip core and I want to distribute it, but I don't want to distribute the source files. I want to distribute it as black box. Example .NGC, .EDIF, ... Somebody know how ?
Because I try to use Xilinx ISE 6.3i make .NGC file, After that create new project, define this module as submodule in VHDL file. It cannot work, the xilinx will optimize this module ??? I don't know and don't understand, why ??

 

[eda_wiz]

how can i make my own ip?

After that create new project, define this module as submodule in VHDL file. It cannot work, the xilinx will optimize this module ??? I don't know and don't understand, why ??

i didnt get ur problem...can you expalin in more detail

 

[liaoliao]

using encryption is better

 

[ikru26]

before ging to make it as IP core ..u have to satisfy wishbone standards..which is normally used for data transfering between systems.

 

[omid219]

convert it to DB format by synopsys's Design Compiler.

 

[nashafi]

Can some one further specify that how to distribute an IP core written in VHDL without realy giving away the VHDL code?

 

[eziggurat]

http://www.fpga-faq.com/archives/43325.html

or type encrypted edif

 

[rprince006]

Most HDL simulators have some command line options for users to encript their HDL source. You may find them in your simulator's user manu.

Regards,
rprince006