How can I make latch or flip-flop from MUX?

[spartanthewarrior]

HI All,

How can i make LATCH from MUX.

and also tell me

That How can i make

Flip-Flop from MUX

 

[research_vlsi]

Re: Latch From MUX



using two mux u can form a flip flop like above..

 

[spartanthewarrior]

Re: Latch From MUX

HI

Can you send me the

Desing for FLIP - FLOP from MUX to...............

 

[research_vlsi]

Re: Latch From MUX

 

[badola]

Re: Latch From MUX

i have one doubt ...do we have a inverted clock as a select line for the second mux???????

 

[sreedhar1983]

Re: Latch From MUX

I think CLK should be inverted for the first MUX

 

[badola]

Re: Latch From MUX

can anyone clear this doubt pls???????which select line should be inverted....first one or second one

 

[research_vlsi]

Re: Latch From MUX

second mux select line should be inverted

 

[nitin_asic]

Re: Latch From MUX

What is the use of 2nd mux??

 

[badola]

Re: Latch From MUX

ya there is no need of second mux.....

 

[carv_13]

Re: Latch From MUX

This should give you a clear understanding. This is a pos edge ff. In the master stage the D input is connected to the 0 of the mux ie during the neg edge of the clock, the D input is latched into the master stage.

In the slave stage, the o/p of master stage is connected to 1 of the mux. Hence during the pos edge of the clock, the o/p of master stage is passed to the o/p of the slave stage which is Q.

There is no need for inverted clock signal.

Hoping that helped

 

[neetinsingh]

Re: Latch From MUX

can anyone clear this doubt pls???????which select line should be inverted....first one or second one

hi

if u make second select line it become negative edge triggered and if first one than it will become positive edge triggered.......

check it using waveforms.......

if u get something else please let me know....

Regards

neetin

Added after 3 minutes:

using two mux u can form a flip flop like above..

hi

can u tell me wht exactly this single mux with the given arrangment represent......is it a latch?????????

 

[research_vlsi]

Re: Latch From MUX

yes its a Latch. what doubt u have in that?

Latch is Level sensitive, so in the diagram B is the select line and A is the D input. u can understand from the wave form easily.


for practical understanding write a verilog code, simulate and see..

 

[neetinsingh]

Re: Latch From MUX

yes its a Latch. what doubt u have in that?

Latch is Level sensitive, so in the diagram B is the select line and A is the D input. u can understand from the wave form easily.


for practical understanding write a verilog code, simulate and see..

i can explain my dobt using following equations

for a mux

output = S' Input0 + S Input1

where S is select line

the diagram which is given if i put it in to above equation it come out to be

output = B' output + B A

now i have a doubt that when B=0 and A=1 the output should be 1 but it comes out to be dependent on feedbacked value of output. if it so than it does not satisfies the latch truth table.

tell me if my analysis is wrong or correct........

 

[dmk]

Re: Latch From MUX

The circuit with one mux is exactly a latch. It means a level-sensitive trigger. When the input is selected, then the output follows its level. When the input is not selected, then the output follows itself (becouse the selected input this time is connected to the output). To make a flip-flop, i.e. an edge-sensitive trigger, you can use the second circuit.

 

[research_vlsi]

Re: Latch From MUX

hi neetinsingh

Latch is a sequential element, were the output value depends on both the present and past value of inputs.

Here in your case Initially, when B is 0 and A is 1. the output will not be 1. the output will be feedback value of Y, say "X". (because Y is unknown initially)

if u try first B as 1 and A as 1, the output will be 1, after that u try different combination for A and B, u will get exact latch operation.

moreover u write a code for this operation and synthesis, the tool which u synthesis will give latch.