how can i improve my PLL?

[gavin168]

Hi, guys,

the Attachment is the PLL loop simulation result. my VCO control voltage look not very stable. how can i improve it? ( my reference clock is 8 MHz. and VCO is working at 200 MHz. the Kvco is about 520 MHz/v, Charepump current is about 4 uA and main cap of LPF is about 150 p)

And the phase error is quite big when PLL is locked. It is from 30 ps to 400 ps. How can i decrease it?

Thank you.

 

[flatulent]

I would suggest that in all designs the oscillator tuning sensitivity be the minimum possible amount. This can be done by paralleling fixed capacitors with a smaller value variable capacitance diode.

This way noise pickup has a smaller effect on jitter.

 

[lvlei0309]

Is your system stable?

 

[knights]

How about the delay cell control voltage. I mean normally , V control will be added
to delay cell through a source follow. The source of this source follow is the acturally control voltage of your delay cells.Suppose your control voltage noise
is 1mv(base on your pic) , the the frequency variation will be 500KHz, so the output frequency will be ,let say, 200.5Mhz.
The peak to peak jitter of clock will be 5n- 4.987n=13p. That is small compare to
other noise source.

 

[saro_k_82]

I smell a stability issue here. What is your bandwidth. Just playing around it should settle the issue. You could do it by changing the charge pump current / feedback N / LPF components.

 

[jeepx5]

Increase the open loop gain to decrease the locked phase error

 

[saro_k_82]

Increase the open loop gain to decrease the locked phase error

This, I guess is Type II PLL., Type I are obsolete today. The steady state error is zero independent of OL gain (Ofcourse as long as the loop is stable).

 

[flutecn]

hi

Maybe there is some loop stability issue in your design because of the large ripple.
According to your design parameters, we can not verify if the loop system is okay.
You should provide the value of the resistor in the LPF yet.