gavin168
Junior Member level 3
Hi, guys,
the Attachment is the PLL loop simulation result. my VCO control voltage look not very stable. how can i improve it? ( my reference clock is 8 MHz. and VCO is working at 200 MHz. the Kvco is about 520 MHz/v, Charepump current is about 4 uA and main cap of LPF is about 150 p)
And the phase error is quite big when PLL is locked. It is from 30 ps to 400 ps. How can i decrease it?
Thank you.
the Attachment is the PLL loop simulation result. my VCO control voltage look not very stable. how can i improve it? ( my reference clock is 8 MHz. and VCO is working at 200 MHz. the Kvco is about 520 MHz/v, Charepump current is about 4 uA and main cap of LPF is about 150 p)
And the phase error is quite big when PLL is locked. It is from 30 ps to 400 ps. How can i decrease it?
Thank you.