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How can I improve my circuit?

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david90

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please see my circuit here

capacitivekey.pdf


Specifically, I'd like some opinions on the open collector output circuit. Pin 3 of J1 will be connected to a car's unlock switch. When Q1 is on, it will unlock a car's door by pulling the car's unlock input to gnd.

In general, what are some improvements that I can make?
 

What is the purpose of R21? If Q1 is supposed to be an open collector output, the R21 is not needed. I am assuming that the pullup resistor for this open collector output is at the other end of the J1 cable.

Open collector is meant to allow communication between systems with different operating voltages. The driver circuit, which is your board, provides the method for asserting a logic LOW, aka Q1 conducting. The receiving circuit is required to provide the means for asserting a logic HIGH by providing a pullup resistor to the appropriate voltage rail.

If the receiving circuit uses a small value pullup resistor like 4.7K, then the 1K resistor R21 will prevent pin3 of J1 from reaching a valid logic LOW. That is why I believe R21 can cause an issue.
 

banjo said:
What is the purpose of R21? If Q1 is supposed to be an open collector output, the R21 is not needed. I am assuming that the pullup resistor for this open collector output is at the other end of the J1 cable.

Open collector is meant to allow communication between systems with different operating voltages. The driver circuit, which is your board, provides the method for asserting a logic LOW, aka Q1 conducting. The receiving circuit is required to provide the means for asserting a logic HIGH by providing a pullup resistor to the appropriate voltage rail.

If the receiving circuit uses a small value pullup resistor like 4.7K, then the 1K resistor R21 will prevent pin3 of J1 from reaching a valid logic LOW. That is why I believe R21 can cause an issue.

R21 is for current limiting just in case somebody directly connect pin 3 of J1 to a 12V source. That will burn Q1. I could see your point in that R21 could prevent PIN3 of J1 from reaching a valid logic low.

How can I design it so that Q1 is current limited for protection but also be able to correctly assert a logic low?
 

Using a fuse is overkill.

When PIN 3 of J1 is low, the current going through Q1 is not a lot (1-3mA).
 

If you are looking to protect Q1 from 12V, then you should increase the base resistor on Q1 to limit the base current and then change R21 to a more reasonable value.

Right now you have about 2mA of base current. Assuming a beta of 100, then Q1 could have up to 200mA of collector current. You do not need all this collector drive. Change R20 to 15K. This keeps the max collector current under 30mA. Now 12V/30mA = 400 ohms. So R21 would go to 400 ohms and Q1 should be able to withstand a 12V input. However, you need to know the value of the pullup resistor on the other end of the cable and you need to know VIL on the input circuit to be assured that you still meet the logic thresholds.
 

david90 said:
please see my circuit here

capacitivekey.pdf


Specifically, I'd like some opinions on the open collector output circuit. Pin 3 of J1 will be connected to a car's unlock switch. When Q1 is on, it will unlock a car's door by pulling the car's unlock input to gnd.

In general, what are some improvements that I can make?

ESD protection ?
 

banjo said:
If you are looking to protect Q1 from 12V, then you should increase the base resistor on Q1 to limit the base current and then change R21 to a more reasonable value.

Right now you have about 2mA of base current. Assuming a beta of 100, then Q1 could have up to 200mA of collector current. You do not need all this collector drive. Change R20 to 15K. This keeps the max collector current under 30mA. Now 12V/30mA = 400 ohms. So R21 would go to 400 ohms and Q1 should be able to withstand a 12V input. However, you need to know the value of the pullup resistor on the other end of the cable and you need to know VIL on the input circuit to be assured that you still meet the logic thresholds.

Thanks for the input. Say that the pull up on the other end of the cable is 10Kohm and VIL = .5V, how would you do the calculation?
 

You did not provide what voltage the 10K resistor pulls the signal up to. Let the pullup voltage be VCC. The open collector output on the pin of the connector will be:

(R21*(VCC-0.2)/(10K + R21)) + 0.2

The 0.2 is the typical value of the collector to emitter voltage of a saturated transistor.

If you assume 5V, I estimate that VOL of the open collector driver will be less than 0.38V.
 

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