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Very interesting, both the links indicate that an asynchronous ram is possible in a xilinx FPGA.
I have gone thro' all virtex family datasheets and all of them indicate that the LUTs provide synchronous RAM.
eg, check virtex datasheet
Page-4, under "Look-Up Tables"
Has anybody used Leonardo Spectrum to develop an asynchronous RAM in these devices? Is it really possible??
It's been many years since I used async RAM, so I could be way off the mark here, but can you not make the Xilinx distributed ram (sync write/async read) look like async RAM by driving the write clock input with your write-enable signal instead of a clock? I mean, even async ram needs some event to tell it to update the ram contents with the value on the input bus - in xilinx distributed ram this would be the rising edge of the clock qualified with the write enable signal. So just tie the xilinx write-enable high and run your "async" write enable into the clock input. There may be set-up and hold timing issues related to this that nee to be considered...