Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How can I implement a asyn ram in Xilinx ?

Status
Not open for further replies.

netghost

Newbie level 3
Joined
Feb 11, 2003
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
78
xilinx clb based projects

How can I implement a asyn ram in Xilinx ?
Does Xilinx only support syn ram?
 

rx300

Member level 3
Joined
Mar 2, 2002
Messages
60
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
650
port a ram enable input xilinx

netghost said:
How can I implement a asyn ram in Xilinx ?
Does Xilinx only support syn ram?
I doubt why you need async RAM. Xilinx RAM is sync write, async read. That has been good enough for me for the past.

rx300
 

bubber1974

Newbie level 3
Joined
Dec 23, 2002
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
26
how to use ram in xillinx

The only way is to use flip flop's (i.e. CLBs)
 

it_boy

Full Member level 3
Joined
Jul 18, 2002
Messages
173
Helped
6
Reputation
12
Reaction score
2
Trophy points
1,298
Activity points
1,261
using ram in xilinx

Hi bubber1974
Do you mean LUTs?
Even LUTs provide synchronous RAM. I dont think Async RAM can be developed with any part of a CLB
 

maestor

Full Member level 3
Joined
Feb 21, 2002
Messages
163
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,298
Location
España
Activity points
1,888
xilinx lut ram

Have a look to these files which were posted a while ago (they have been deleted or something),

They are talking about asynchronous FIFOs and might help you.

Regards,

-Maestor
 

E-goe

Member level 5
Joined
Jan 10, 2003
Messages
84
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
715
fifo+xilinx+pdf

There is an application note on the Xilinx website

h**p://www.xilinx.com/xapp/xapp065.pdf

Check it out

Greetz E-goe
 

aramis

Member level 3
Joined
Apr 7, 2002
Messages
64
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
418
asynchronous sram xilinx

why not use CoreGen to produce a asyn ram??
 

it_boy

Full Member level 3
Joined
Jul 18, 2002
Messages
173
Helped
6
Reputation
12
Reaction score
2
Trophy points
1,298
Activity points
1,261
xilinx lutram

I dont think there's any option to generate async RAM using Coregen. Yes, asynchronous fifo can be developed.
 

leon

Junior Member level 1
Joined
May 20, 2003
Messages
17
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
430
xilinx asynchronous fpga

Asyn-Fifo is different asyn-RAM.
Asyn-fifo means that the output port can use a differnt clock other than than the input data port.
But asyn-ram does not need any clock.
 

dada

Member level 1
Joined
Jun 10, 2002
Messages
37
Helped
4
Reputation
8
Reaction score
4
Trophy points
1,288
Activity points
185
xilinx memory write enable read enable

it has to be genrated by using only CLB`s (combo) .
dada
 

Zerox100

Full Member level 6
Joined
Mar 1, 2003
Messages
320
Helped
21
Reputation
42
Reaction score
10
Trophy points
1,298
Activity points
2,508
qualified write enable xilinx

dada said:
it has to be genrated by using only CLB`s (combo) .
dada
_http://www.xilinx.com/xcell/xl32/xl32_34.pdf
_http://www.msa.cmst.csiro.au/projects/clps/clp/xilinx/ccgl_libs/ccgl_libs.html
 

it_boy

Full Member level 3
Joined
Jul 18, 2002
Messages
173
Helped
6
Reputation
12
Reaction score
2
Trophy points
1,298
Activity points
1,261
asynchronous ram in core gen

Zerox100 said:
dada said:
it has to be genrated by using only CLB`s (combo) .
dada
_http://www.xilinx.com/xcell/xl32/xl32_34.pdf
_http://www.msa.cmst.csiro.au/projects/clps/clp/xilinx/ccgl_libs/ccgl_libs.html
Very interesting, both the links indicate that an asynchronous ram is possible in a xilinx FPGA.
I have gone thro' all virtex family datasheets and all of them indicate that the LUTs provide synchronous RAM.
eg, check virtex datasheet
hxxp://direct.xilinx.com/bvdocs/publications/ds003-2.pdf
Page-4, under "Look-Up Tables"
Has anybody used Leonardo Spectrum to develop an asynchronous RAM in these devices? Is it really possible??
 

haifengyuyun

Member level 1
Joined
May 7, 2003
Messages
37
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
207
asyn ram

and i know coregen can only gen syn ram ,so i use part syn ram is ok;i think it is not thnigs of compiler
 

Al Farouk

Full Member level 4
Joined
Jan 13, 2003
Messages
191
Helped
16
Reputation
32
Reaction score
16
Trophy points
1,298
Location
Egypt
Activity points
1,854
asynchronous sram implementation in fpga

check xilinx application notes and FPGA-Fac site
 

juggernaut

Member level 1
Joined
Jan 25, 2002
Messages
33
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
346
xilinx fpga ram

It's been many years since I used async RAM, so I could be way off the mark here, but can you not make the Xilinx distributed ram (sync write/async read) look like async RAM by driving the write clock input with your write-enable signal instead of a clock? I mean, even async ram needs some event to tell it to update the ram contents with the value on the input bus - in xilinx distributed ram this would be the rising edge of the clock qualified with the write enable signal. So just tie the xilinx write-enable high and run your "async" write enable into the clock input. There may be set-up and hold timing issues related to this that nee to be considered...

J
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top