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How can I implement a asyn ram in Xilinx ?

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Feb 11, 2003
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xilinx clb based projects

How can I implement a asyn ram in Xilinx ?
Does Xilinx only support syn ram?

port a ram enable input xilinx

netghost said:
How can I implement a asyn ram in Xilinx ?
Does Xilinx only support syn ram?

I doubt why you need async RAM. Xilinx RAM is sync write, async read. That has been good enough for me for the past.


how to use ram in xillinx

The only way is to use flip flop's (i.e. CLBs)

using ram in xilinx

Hi bubber1974
Do you mean LUTs?
Even LUTs provide synchronous RAM. I dont think Async RAM can be developed with any part of a CLB

xilinx lut ram

Have a look to these files which were posted a while ago (they have been deleted or something),

They are talking about asynchronous FIFOs and might help you.




There is an application note on the Xilinx website


Check it out

Greetz E-goe

asynchronous sram xilinx

why not use CoreGen to produce a asyn ram??

xilinx lutram

I dont think there's any option to generate async RAM using Coregen. Yes, asynchronous fifo can be developed.

xilinx asynchronous fpga

Asyn-Fifo is different asyn-RAM.
Asyn-fifo means that the output port can use a differnt clock other than than the input data port.
But asyn-ram does not need any clock.

xilinx memory write enable read enable

it has to be genrated by using only CLB`s (combo) .

qualified write enable xilinx

dada said:
it has to be genrated by using only CLB`s (combo) .


asynchronous ram in core gen

Zerox100 said:
dada said:
it has to be genrated by using only CLB`s (combo) .


Very interesting, both the links indicate that an asynchronous ram is possible in a xilinx FPGA.
I have gone thro' all virtex family datasheets and all of them indicate that the LUTs provide synchronous RAM.
eg, check virtex datasheet
Page-4, under "Look-Up Tables"
Has anybody used Leonardo Spectrum to develop an asynchronous RAM in these devices? Is it really possible??

asyn ram

and i know coregen can only gen syn ram ,so i use part syn ram is ok;i think it is not thnigs of compiler

asynchronous sram implementation in fpga

check xilinx application notes and FPGA-Fac site

xilinx fpga ram

It's been many years since I used async RAM, so I could be way off the mark here, but can you not make the Xilinx distributed ram (sync write/async read) look like async RAM by driving the write clock input with your write-enable signal instead of a clock? I mean, even async ram needs some event to tell it to update the ram contents with the value on the input bus - in xilinx distributed ram this would be the rising edge of the clock qualified with the write enable signal. So just tie the xilinx write-enable high and run your "async" write enable into the clock input. There may be set-up and hold timing issues related to this that nee to be considered...


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