CMOS-Tangram
Junior Member level 1
Hi to all!
I have been designing an amplifier + Test Buffer (50 Ohm) for a company and now I have to send my first results. This design has been developed in cadence.
My question is:
Is there any way to create a symbol that reproduces the circuit behavior but hides the netlist?
Greetings and thanks in advance!
I have been designing an amplifier + Test Buffer (50 Ohm) for a company and now I have to send my first results. This design has been developed in cadence.
My question is:
Is there any way to create a symbol that reproduces the circuit behavior but hides the netlist?
Greetings and thanks in advance!