How can I generate a VCD file?

Mamdouh · May 5, 2010

VCD file

How can I generate a VCD file?

nsingh95 · May 5, 2010

Re: VCD file

Mamdouh said:
How can I generate a VCD file?

Hi,
Inorder to generate a vcd file , you have to use following key words in your test bench file ... ie <testbench top filename.v>:
type :

initial
dumpfile("module_name.vcd");
initial
dumpvars();

If you simulate with this logic you will surely get the vcd file.

balavinayagam · May 5, 2010

open terminal and load ur verilog file (cd /cad ...cd <filename>)
then type
"vcs <pathname> <pathname of testbench> + v2k -debug_all
`/simv-gui"
waveform is generated
right click on the schematic,add to wave simulator_start

then .vcd file is generated

vivek_p · May 5, 2010

$dumpvars;

Paste this in ur test bench

Mamdouh · May 6, 2010

nsingh95 said:
Hi,
Inorder to generate a vcd file , you have to use following key words in your test bench file ... ie <testbench top filename.v>:
type :

initial
dumpfile("module_name.vcd");
initial
dumpvars();

If you simulate with this logic you will surely get the vcd file.

how can i write these lines in vhdl format

Added after 1 hours 4 minutes:

to be specific i want to generate vcd file from testbench.vhd using xilinx ?

nsingh95 · May 6, 2010

Mamdouh said:
nsingh95 said:

Hi,
Inorder to generate a vcd file , you have to use following key words in your test bench file ... ie <testbench top filename.v>:
type :

initial
dumpfile("module_name.vcd");
initial
dumpvars();

If you simulate with this logic you will surely get the vcd file.

Click to expand...

how can i write these lines in vhdl format

Added after 1 hours 4 minutes:

to be specific i want to generate vcd file from testbench.vhd using xilinx ?

Hi,
Please see the section 11 of the attached pdf. All your issues will be resolved.

Mamdouh · May 6, 2010

first thanks very much i used the commands in the manual and here's the generated vcd file i know there's something wrong but i cant figure it out??

$comment
File created using the following command:
vcd file ana.vcd -dumpports

$end
$date
Thu May 06 22:35:44 2010
$end
$version
dumpports ModelSim Version 6.5
$end
$timescale
1ps
$end
$vcdclose
#1000
$end

nsingh95 · May 7, 2010

Mamdouh said:
first thanks very much i used the commands in the manual and here's the generated vcd file i know there's something wrong but i cant figure it out??

$comment
File created using the following command:
vcd file ana.vcd -dumpports

$end
$date
Thu May 06 22:35:44 2010
$end
$version
dumpports ModelSim Version 6.5
$end
$timescale
1ps
$end
$vcdclose
#1000
$end

Click to expand...

Hi,
Please let me know the issue you are facing.

jassen · Jul 16, 2010

There are easy to get the methods from VCS manual.

cvc · Jul 18, 2010

Mamdouh said:
first thanks very much i used the commands in the manual and here's the generated vcd file i know there's something wrong but i cant figure it out??

$comment
File created using the following command:
vcd file ana.vcd -dumpports

$end
$date
Thu May 06 22:35:44 2010
$end
$version
dumpports ModelSim Version 6.5
$end
$timescale
1ps
$end
$vcdclose
#1000
$end

Click to expand...

It looks like there was no activity on your signals hence the VCD file is empty of "value changes". Did you see a waveform in Modelsim? If so do you have a vsim.wlf file created? If yes you may also use

Code:

wlf2vcd (or something similar)

to create VCD out of WLF file.

Regards
TeamCVC
www.cvcblr.com/blog

How can I generate a VCD file?

Mamdouh

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nsingh95

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Mamdouh

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