How can I determine the order of FIR filter if it has 8-taps?

Similar threads

• A

  How can I run verilog code with data at a specific time in the past?

  • Started by alexis57
  • Jan 28, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• K

  small value FIR coefficients

  • Started by kaz1
  • Feb 1, 2024
  • Replies: 4

  PLD, SPLD, GAL, CPLD, FPGA Design
• O

  Laplacian filter

  • Started by Omar21
  • Apr 4, 2024
  • Replies: 3

  PLD, SPLD, GAL, CPLD, FPGA Design
• Z

  [SOLVED] Why "The Memory Controller has one address channel?"

  • Started by zzzhhh
  • Jun 20, 2023
  • Replies: 1

  PLD, SPLD, GAL, CPLD, FPGA Design
• [SOLVED] object cannot be indexed because it has natural type rather than array type

  • Started by rafimiet
  • Jan 30, 2023
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design