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IC technology is continuing to scale according to Moore’s
Law, with the overall chip circuit requirements driving the
MOSFET device and process integration requirements and
In the 2001 ITRS the driver for the high
performance logic is maximizing MOSFET intrinsic speed,
while the driver for low power logic is minimizing
MOSFET leakage current. The rapid increase in off state
sub-threshold leakage and gate tunneling currents due to
device scaling for more performance may be controlled by
utilizing multi Vt and multi gate oxide transistors and by
utilizing device/design/architectural techniques such as well
biasing and power down/reduction.