library ieee;
use ieee.std_logic_1164.all;
entity ROM is
port ( address : in std_logic_vector(3 downto 0);
data : out std_logic_vector(7 downto 0) );
end entity ROM;
architecture behavioral of ROM is
type mem is array ( 0 to 2**4 - 1) of std_logic_vector(7 downto 0);
constant my_Rom : mem := (
0 => "00000000",
1 => "00000001",
2 => "00000010",
3 => "00000011",
4 => "00000100",
5 => "11110000",
6 => "11110000",
7 => "11110000",
8 => "11110000",
9 => "11110000",
10 => "11110000",
11 => "11110000",
12 => "11110000",
13 => "11110000",
14 => "11110000",
15 => "11110000");
begin
process (address)
begin
case address is
when "0000" => data <= my_rom(0);
when "0001" => data <= my_rom(1);
when "0010" => data <= my_rom(2);
when "0011" => data <= my_rom(3);
when "0100" => data <= my_rom(4);
when "0101" => data <= my_rom(5);
when "0110" => data <= my_rom(6);
when "0111" => data <= my_rom(7);
when "1000" => data <= my_rom(8);
when "1001" => data <= my_rom(9);
when "1010" => data <= my_rom(10);
when "1011" => data <= my_rom(11);
when "1100" => data <= my_rom(12);
when "1101" => data <= my_rom(13);
when "1110" => data <= my_rom(14);
when "1111" => data <= my_rom(15);
when others => data <= "00000000";
end case;
end process;
end architecture behavioral;
skycanny said:hi,Renjith:
I am trying to implement a DDS and using Xilinx FPGA.
However, I do not want to use CoreGen because the module CoreGen creates is hard to migrate to other target device.
library ieee;
use ieee.std_logic_1164.all;
entity ROM is
port ( clk : in std_logic;
e : in std_logic;
r : in std_logic;
data : out std_logic_vector(7 downto 0) );
end entity ROM;
architecture behavioral of ROM is
signal i: integer range 0 to 6063:=0;
signal enable : STD_LOGIC:='0';
type mem is array ( 0 to 6063) of std_logic_vector(7 downto 0);
constant my_Rom : mem :=
DATA HERE...
...
...
...
moreins said:/.../problem now is that when synthetizing in ise,
this takes almost 40 minutes/.../
process(clk)
begin
if(rising_edge(clk)) then
q <= my_Rom(addr); <=======
end if;
end process;
library ieee;
use ieee.std_logic_1164.all;
entity ROM is
port ( clk : in std_logic;
e : in std_logic;
r : in std_logic;
data : out std_logic_vector(7 downto 0) );
end entity ROM;
architecture behavioral of ROM is
signal i: integer range 0 to 6063:=0;
signal enable : STD_LOGIC:='0';
type mem is array ( 0 to 6063) of std_logic_vector(7 downto 0);
constant my_Rom : mem := (
"10000011",
"10000100",
"10000101",
"10000011",
....
....
....
....
...
....7000 more lines
);
begin
process(e)
begin
if e'event and e='1' then
enable<='1';
end if;
end process;
process(clk)
begin
if r = '1' then
data <="00000000";
elsif enable='1' then
if clk'event and clk='1' then
data<=my_rom(i);
i<=i+1;
end if;
end if;
end process;
end architecture behavioral;
entity rom is
port
(
clk : in std_logic;
e : in std_logic;
r : in std_logic;
data_out: out std_logic_vector (7 downto 0)
);
end rom;
architecture rtl of rom is
signal i : integer range 0 to 7:=0; -- change the range value
signal enable : std_logic:='0';
signal data : std_logic_vector (7 downto 0);
BEGIN
process (e) -- i don't like this, would be better
begin -- to use clk as a sync. signal
if e'event and e = '1' then
enable <= '1';
end if;
end process;
process ( clk)
begin
if rising_edge (clk) then
if (enable = '1') then
i <= i + 1;
end if;
end if;
end process;
process (clk)
begin
if rising_edge (clk) then
case i is
when 0 => data <= "10111100";
when 1 => data <= "11011001";
when 2 => data <= "00000111";
when 3 => data <= "10101000";
when 4 => data <= "10101001";
when 5 => data <= "10101000";
when 6 => data <= "10101011";
when 7 => data <= "10110010";
-- .... fill in the correct values here for larger 'i' index
end case;
end if;
end process;
process (r,data)
begin
if r = '1' then data_out <= "00000000";
else data_out <= data;
end if;
end process;
END rtl;
if r = '1' then
data <="00000000";
elsif enable='1' then
if clk'event and clk='1' then
data<=my_rom(i);
i<=i+1;
end if;
end if;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity single_port_rom is
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 8
);
port
(
clk : in std_logic;
addr : in natural range 0 to 2**ADDR_WIDTH - 1;
q : out std_logic_vector((DATA_WIDTH -1) downto 0)
);
end entity;
architecture rtl of single_port_rom is
-- Build a 2-D array type for the RoM
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
function init_rom
return memory_t is
variable tmp : memory_t := (others => (others => '0'));
begin
for addr_pos in 0 to 2**ADDR_WIDTH - 1 loop
-- Initialize each address with the address itself
tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, DATA_WIDTH));
end loop;
return tmp;
end init_rom;
-- Declare the ROM signal and specify a default value. Quartus II
-- will create a memory initialization file (.mif) based on the
-- default value.
signal rom : memory_t := init_rom;
begin
process(clk)
begin
if(rising_edge(clk)) then
q <= rom(addr);
end if;
end process;
end rtl;
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