How Can I Build a Digital Clock Manager In VHDL

ishailesh · Apr 17, 2012

Hey All

I am trying my hand at VHDL. So the task that i am supposed to do is to built a digital clock manager.
How can i implement it. What should be its structure look like?
How can i connect its different module?

Regards

sumansamui · Apr 17, 2012

what are those different modules?

ishailesh · Apr 17, 2012

sumansamui said:
what are those different modules?

Sir,

The module which i will be using are

1. Digital Frequency Synthesizer (Programmable Multiplier / Divider )
2. Duty Cycle Corrector
3. Programmable phase shifter
4. Programmable duty cycle synthesizer
5. Coarse Phase Shifter

Regards

ravics · Apr 17, 2012

Seems to be a complex task. Clock dividers are easy to code in VHDL/Verilog.

TrickyDicky · Apr 17, 2012

ravics said:
Seems to be a complex task. Clock dividers are easy to code in VHDL/Verilog.

And should not be used to clock logic.

If you are refering to xilinx DCMs, you have to instantiate them in your code. You cannot create them from VHDL because they contain all sorts of analogue logic.

How Can I Build a Digital Clock Manager In VHDL

ishailesh

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