How calculate adress decoder

[send]

I need to build in EW the memory block P-ROM 1kb with chips 256*8. So i understand that there should be 4 chips that should be connected in consecutive way. The adresses include the A0.A6. But this chip should be connected with adress decoder with other A7.A15 to 16 bit bus. So i need to build the 4 CS inputs from decoder. But do not have algorytm. Despite I have an example to do it with 2kb*8 with 2 1kb*8. We should define base and end adress with two second variants. But how. Is it done random. For example there is such code. Base ad:11100 and other eleventh zeros. The end a:11100with other eleventh "1". How it is defined? And how to translate it to my case. Then i need to build chat with logic expression based on it that should be much easier if i would have the base and end adress.

 

[barry]

I don't quite understand, none of your numbers make sense. 1kb? A0.A6? 256x8 is 2kb and require 8 address lines, not 7. Four 256x8 chips don't need 16 bit address bus-you just need 10 bits.

Maybe what you are trying to say is that you have four 256x8 bit ROMS? In that case you would need address A0-A7 going to the address inputs of all four chips. Then you would decode A8 and A9 to get your 4 chip selects, i.e.

A9 A8
0 0 -->CS0
0 1 --> CS1
1 0 --> CS2
1 1 --> CS3

 

[send]

I don't quite understand, none of your numbers make sense. 1kb? A0.A6? 256x8 is 2kb and require 8 address lines, not 7. Four 256x8 chips don't need 16 bit address bus-you just need 10 bits.

Maybe what you are trying to say is that you have four 256x8 bit ROMS? In that case you would need address A0-A7 going to the address inputs of all four chips. Then you would decode A8 and A9 to get your 4 chip selects, i.e.

A9 A8
0 0 -->CS0
0 1 --> CS1
1 0 --> CS2
1 1 --> CS3

Yes, you are right that chips should have afress line A0..A7. It is my ommision with one line. Maybe you are also right about that we need the 10bit bus. But teacher drawed for 1kb chip that should be also included to 10 adress line but it is connected with 16 bit with decoder. So 256*8 means the capacity of chip with 8 bit in every cell so of cause it need the 8 output line. This chips should comprise memory with 1kb-kilobytes. I understand that also with 8bit in mach one. If we need only two additional lines a8 and a9 it seems very simple. That decoder has four different combination of 1 and 0. After that i need to write logical expression in disunction or conjunction brief normal function. After it i need to draw this decoder with I understand according to you with two inputs and four outputs. How to calculate it graphical form? It would be very helpful how to do if you cs calculation is true.

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So my main question related to calculation of code in decoder. 11,10, 01, 00 is easy as it doesnt suppose any other combination for 4 chip selects. But if it needs 16 lines how to decode it that case to understand it better as 1kb chip that is only for two levels larger is synthesed with 16 bit bus. So if i need only 10 bit how to graphically build the adress decoder. With using "and" or "or" elements and "no" clements.

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So my main question related to calculation of code in decoder. 11,10, 01, 00 is easy as it doesnt suppose any other combination for 4 chip selects. But if it needs 16 lines how to decode it that case to understand it better as 1kb chip that is only for two levels larger is synthesed with 16 bit bus. So if i need only 10 bit how to graphically build the adress decoder. With using "and" or "or" elements and "no" clements.

 

[barry]

I'm afraid I still don't understand. Why do you need to use 16 bits when 10 are adequate? You can just ignore the upper six bits.

And you keep saying 1kb chips, when they are 2K-BYTE (256 x 8=2048 NOT 1024!!!!)

 

[send]

Why not 11bit bus-despite it doesnot exist. I am not very strong in sxemotechnics but teacher said that you will not find the scheme of building of memory block. So i have only a sample. It is about 1kb but it also should be contained in 10bit bus but it is connected with 16 bit bus. Let it be. But where i can find the algorith how to calculate the afress decoder or selector. If it is right how the afress decoder should look like-there is only code of decoder.

 

[send]

https://electronix.ru/forum/index.php?showtopic=108227__despite in russian this site has one image with adress decoder in left side for 1kb*8bit (this forum theme has two page so image is on p.1 or p.2./ would you show how to make this AD (4 chip 256 with 4 CS) in logical scheme?

 

[send]

I have such question beside decoder. Is there such chip as 256 bit with 8 cells in it. I need the description of it and how to switch it up to processor kb580.2. What is the command bus in prom as cs is going to decoder, and there is no write enable but should it need to be with output enable.

 

[send]

Would you tell me about the existing 256 bit PROM. What any. I need at least one example. Cause i need to describe it.