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How Buffers will reduce delays

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Newbie level 6
Aug 14, 2009
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Please can any one explain me with derivations (formulas) How adding buffers in a long Path (net) will reduce the delays?

A <------------------------->B (path having 500ps)

now adding buffer in the path (Fanout of A is one, no problem with fanout)

A<--------|>----------->B (path delay reduced to 200ps) how?

Please explain

i dont have formulas .. but logic is this:
buffers increases drive strength of signal and so delay decreases .. this is like a repeater in a communication systems .. where repeater will re-shape the signal to match it to ideal one and thus time taken by signal to transition from 1->0 and 0->1 decreases ..

hope it helps ...


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Thank you, I answered the same as you mentioned in an interview.
But they asked counter question how can you prove.

Thanks lot for giving good explaination.

can you share which company's interview was that? and what other questions did they ask??

Tpd = (Tpf + Tpr)/2
Tpf = 2.2*rn * cout + K*cin
Tpr = 2.2*rp *cout + K*cin

(to derive above equation please refer your graduation book)

Where cout is capacitance seen by output of any logic gate (which in turn would be equal to cin of following gate) ...
cin is input capacitance of any logic gate ...
rn is channel resistance of Nmos and rp is channel resistance of Pmos ...
and k is constant

So Tpd (propogation delay) is dependant on output load (capacitance) seen by a gate and on input capacitance of that gate itself ...

For buffer, cin would be less than typical gates .. buffer design would be made in such a way that its cin would be less than typical gates ...

so delay from A to I decreases .. because delay from A to I would be dependnat on output capacitance seen by A (which is equivalent to cin of buffer and which in turn is lesser (its charactaristics of buffer) than cin of b) .. which is less now and so less delay from A to point I ..

now from point I to b .. delay would be proportional to cin (of I) and cout (of I which is equivalent to cin of B) .. cout is assumed to be large value but as said above cin of buffer is less than typical gates and so delay from I to B is also less than typical gate delays ..

In short, buffer does impedance matching and decreases delay ...

Hope this proves ...

Added after 9 minutes:

also please look at transient (AC) analysis not DC ...


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The funda is simple. If you insert the buffer, the signal strength will be improved. This will charge the load Cap fast. When the Cap gets charged fast, u have less rise & fall delay..This will reduce the delay..thats it.


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yep, kumar is right,
delay of any cell depends on input slew and o/p load ,
when we insert buffer in the net , it divides the cap, that improves output load at driving cell , which intern improves delay of driving cell and even the slew, and as the slew on the net imporves delay will come down,

insert buffer will not always reduce delays.
decrese the load cap. can decrease the cell delay. until the load cap. is much smaller than the output cap. of the cell itself, the delay will nearly not change at all. we can call the delay instrinsic delay.
if a timing path consists of cells with instrinsic delay, insert buffer will just increase the delay.

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