The progress of semiconductor technology in recent decades was mainly due to scaling - proportional reduction of transistor geometrical features: gate length, gate oxide thickness, junction depth, etc. As the dimensions scale down, we need to reduce applied voltages - to preserve device reliability (too high gate voltage will cause oxide breakdown, too high drain voltage will cause hot carrier degradation, etc.). As the electric field is held approximately constant, the device performance (drive current per unit gate width) stays approximately constant, but the device density (number of devices per unit area) is increased. Device threshold voltage does not scale much, since the leakage should stay low (source-drain leakage current is proportional to exp(-Vt/kT)).
These days, the thicknesses became so small, that further scaling is practically prohibited (i.e. there is very high gate oxide leakage due to quantum mechanical tunneling of carriers through ~10A thick gate oxide), That's why semiconductor companies are looking at other alternatives to improve the performance - such as metal gates (to replace polysilicon gates that are prone to depletion effect), high-K dielectrics (to increase physical gate oxide thickness to suppress tunneling bu keeping electrical thickness low), strained Si - to improve carrier mobility, etc.
The scaling of supply voltage has practically stopped at ~1.0V (maybe 0.9 or 0.8V) - due to stability, noise immunity, and other effects.