How are we calculating the setup time & hold time of a f

[kumar_eee]

Setup & Hold

Hi,
How we are calculating the setup time & Hold time of a flop?.

Kumar

 

[master_picengineer]

Setup & Hold

Hi Kumar_eee,

 

[kumar_eee]

Re: Setup & Hold

@master_picengineer,
I don't see any relative info from your post for my question.

 

[soloktanjung]

Re: Setup & Hold

hi,

hope this helps.



regards,
hairo[/url]

 

[master_picengineer]

Re: Setup & Hold

@master_picengineer,
I don't see any relative info from your post for my question.

Sorry it was the wrong book.
I remember a book that discuss this issue as well as signal integrity. Sorry I forget it's title.

 

[kumar_eee]

Re: Setup & Hold

@hairo,
I'm looking for something else. Normally we specify Tsetup=4ns, now I want to know how this 4ns calculated for this flop?.

Anyhow, Thanks for your effort.

Kumar

 

[soloktanjung]

Re: Setup & Hold

hi,

this also.

regards,

 

[kumar_eee]

Re: Setup & Hold

Thanks alot for this doc.. If you have more docs, please upload here...

 

[Amruth]

Re: Setup & Hold

pls go thru morris mano book
i think it is in second chapter
ull get clear cut idea abt that

i hope ull get there

 

[vlsitechnology]

Setup & Hold

I think it depends upon the slew and output load bcz flip flop also has std cells right?
Reply me
Thanks

 

[Amruth]

Re: Setup & Hold

yes it depends on slew & load but its not correct ans 4 his Ques

we can constructs FF wit min six Nand gates right

wit two stages 1st stage contains 4 nand & 2nd contains 2

i/p's & clk is given in 1st stage right

setup = propagation delay of two Nands in 1st stage

hold =propagation delay of one Nand in 2nd stage

thats y hold is alwaz less than setup

i hope itll help u

if u r unable to understand pls go thru Morris Mano

 

[ushasree.t]

Re: Setup & Hold

refer this i hope it will help u